ISL8115EVAL1Z Renesas

Application Note 1881 Author: Billy Yang ISL8115EVAL1Z Synchronous Buck Converter User Guide Introduction ISL8115 Key Features The ISL8115EVAL1Z is a Synchronous Buck Converter Wide V range operation: 2.97V to 36V up to 5.5V output IN implementing Intersils wide input range PWM controller and 30A load current per phase. ISL8115. Utilizing voltage mode control with input Fast transient response feed-forward, the ISL8115EVAL1Z maintains a constant loop - Voltage-mode PWM leading-edge modulation with gain for optimal transient response, especially for applications non-linear control with a wide input voltage range. For a more detailed -Input voltage feed-forward description of the ISL8115 functionality, refer to the ISL8115 data sheet. Integrated 5V high speed 4A MOSFET gate drivers - Internal bootstrap diode This application note includes the test setup, typical performance waveforms, schematic, layout and Bill of Oscillator programmable from 150kHz to 1.5MHz Materials (BOM). - Frequency synchronization to external clock signal Evaluation Board Specifications Diode emulation mode for light load efficiency improvement TABLE 1. EVALUATION BOARD ELECTRICAL SPECIFICATIONS Output OVP/UVP OCP and OTP SPEC DESCRIPTION MIN TYP MAX UNIT Power-good open drain output V Board Input Range 10 12 15 V IN Adjustable soft-start V Output Voltage 1.5 V OUT Pre-bias start-up function I Output Rated Current 30 A OUT Excellent output voltage regulation - 0.6V 1.0% internal reference (-40C~125C) I Overcurrent Threshold 32 A OC - 0.6V 0.7% internal reference (-40C~105C) F Switch Frequency 220 kHz sw - Differential voltage sensing Input UVP Rising threshold 9.7 V Applications Falling threshold 9.2 V Power supply for datacom/telecom and POL Efficiency at 50% load 90.88 % Wide input voltage range buck regulators High current density power supplies RF power amplifier bias compensation Recommended Equipment Input power source up to 15V supply voltage with 60W power supply ability Electronic load with 50W power sinking ability Voltmeters and ammeters 100MHz quad-trace oscilloscope FIGURE 1. ISL8115EVAL1Z EVALUATION BOARD September 25, 2013 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas LLC 2013. All Rights Reserved AN1881.1 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.Application Note 1881 FIGURE 2. ISL8115EVAL1Z TEST SET-UP Quick Test Setup Design Guide 1. Ensure that the Evaluation board is correctly connected to the The ISL8115EVAL1Z is optimized for 10V to 15V input voltage power supply and the electronic load prior to applying any range. However, the evaluation board can be modified to support power. Please refer to Figure 2 for proper set-up. multiple applications due to the customer requirements. Please refer to the datasheet for the detailed information. 2. Set the input voltage to 12V, turn on the power supply and observe output voltage. The output voltage should variation Output Voltage Adjustment should be within 5%. The output voltage can be set by the resistor R4, R1. In order to 3. Adjust load current within 30A. The output voltage variation keep the existing compensation parameters unchanged, adjust should be within 5%. R4 to set the output voltage by the following Equation 1: 4. Use oscilloscope to observe output ripple voltage and phase 0.6V R1 node ringing. For accurate measurement, please refer to (EQ. 1) R4 = Figure 3 for proper set-up. Vout 0.6V Note: Test points TP1 TP3 TP8 TP9 are for voltage VMON monitors the output for UVP and OVP, the resistor divider measurement only. Do not allow high current through these test value of R11/R8 should be the same with the R1/R4. points. Synchronization Probe Set-up ISL8115EVAL1Z board can be synchronized with an external clock. Apply a clock signal (10% to 90% duty cycle) in the range of 150kHz to 1.5MHz to the FSET pin makes the internal frequency synchronized with the external clock. Please remove R27 when the sync function is implemented. FIGURE 3. OSCILLOSCOPE PROBE SET-UP AN1881.1 2 September 25, 2013