DATASHEET ISL85005, ISL85005A FN8871 Rev.2.00 4.5V to 18V Input, 5A High Efficiency Synchronous Buck Regulator May 17, 2018 The ISL85005 and ISL85005A are monolithic, synchronous Features buck regulators with integrated 5A, 18V high-side and low-side 4.5V to 18V input voltage range FETs. These devices provide an integrated bootstrap diode for the high-side gate driver to reduce the external parts count. Internal 5A, 18V high-side and low-side MOSFET switches These devices also have a wide input voltage range to support 1%, 0.8V feedback voltage reference applications with input voltage from multi-cell batteries or Integrated bootstrap diode with undervoltage detection regulated 5V and 12V power rails. Current mode control with internal slope compensation The ISL85005 and ISL85005A regulate the output voltage with current mode control and have an internal oscillator. The Internal or external compensation options switching frequency of the ISL85005 is internally set as Default internally set 500kHz switching frequency 500kHz, and can be synchronized to an external clock signal Synchronization capability to external clock (ISL85005) with frequency ranges from 300kHz to 2MHz. The ISL85005A has a fixed 500kHz switching frequency. Diode Emulation Mode (DEM) and Forced CCM (FCCM) options (ISL85005) The ISL85005 has a fixed 2.3ms soft-start, while the Adjustable soft-start time (ISL85005A) ISL85005A features programmable soft-start to limit inrush Output Power-Good (PG) indicator current during startup. With the SS pin floating, the soft-start time of ISL85005A is also 2.3ms. Input Undervoltage Lockout (UVLO), input and output overvoltage protection The ISL85005 can be configured in either forced Continuous High-side cycle-by-cycle current limit, low-side forward and Conduction Mode (CCM) or Diode Emulation Mode (DEM). DEM reverse overcurrent protection, and thermal shutdown enables high efficiency at light-load conditions. The ISL85005A always operates in forced CCM. Small 12-pin 3mmx4mm Dual Flat No-Lead (DFN) package with EPAD for enhanced thermal performance The ISL85005 and ISL85005A have built-in protections including input UVLO protection, input and output overvoltage Applications protection, high-side cycle-by-cycle current limit, low-side Network and communications equipment forward current limit and reverse current limit, and thermal shutdown. Battery powered systems Multifunction printers Related Literature Point-of-load regulators For a full list of related documents, visit our website Standard 12V rail supplies ISL85005, ISL85005A product pages Embedded computing systems Typical Application 95 90 ISL85005 GND = DEM VCC = FCCM 85 SYNC/ MODE 1 BOOT 12 MODE C 4 V IN 80 VDD PG 2 PG 11 4.5V TO 18V EN 3 EN VIN 10 75 PGND VIN 4 FB 9 C C 3 C 6 70 5 V R 2 OUT 5 COMP PHASE 8 12V TO 5V R 1 5A MAX 65 C 1 AGND 6 PHASE 7 12V TO 3.3V L 1 60 C C 8 9 12V TO 1.8V 55 50 01 2345 OUTPUT CURRENT (A) FIGURE 1. ISL85005 WITH INTERNAL COMPENSATION FIGURE 2. EFFICIENCY vs OUTPUT CURRENT FN8871 Rev.2.00 Page 1 of 23 May 17, 2018 EFFICIENCY (%)ISL85005, ISL85005A Table of Contents Typical Application 1 Functional Block Diagram 3 Pin Configurations . 4 Pin Descriptions . 4 Ordering Information 5 Typical Application Schematics 6 Absolute Maximum Ratings . 7 Thermal Information . 7 Recommended Operating Conditions 7 Electrical Specifications . 7 Typical Characteristics . 9 Typical Performance Curves . 11 Detailed Description 15 Operation Initialization 15 FCCM Control Scheme . 15 Light-Load Operation . 15 Synchronization Control 15 Enable, Soft-Start, and Disable 16 Output Voltage Selection . 16 Protection Features . 16 Forward Overcurrent Protection 16 Reverse Overcurrent Protection 16 Output Overvoltage Protection . 16 Input Overvoltage Protection 16 Thermal Overload Protection 16 Power Derating Characteristics 16 Application Guidelines 17 Boot Undervoltage Detection 17 Switching Regulator Output Capacitor Selection 17 Output Inductor Selection . 18 Input Capacitor Selection . 18 Loop Compensation Design . 19 Compensator Design Goal . 19 High DC Gain . 19 Layout Considerations 19 Revision History 21 Package Outline Drawing 22 FN8871 Rev.2.00 Page 2 of 23 May 17, 2018