DATASHEET ISL8723, ISL8724 FN6413 Rev 1.00 Power Sequencing Controllers April 22, 2009 The Intersil ISL8723 and ISL8724 are 4 channel sequencers Features controlling the on and off sequence of voltages with Enables arbitrary turn-on and turn-off sequencing of up to undervoltage supply fault protection and a sequence four power supplies (0.7V to 5V) completed signal (RESET). For larger systems, more than 4 Operates from 2.5V to 5V supply voltage voltages can be sequenced by a simple connection of multiple IC s. These sequencers use an integrated charge Supplies V +5.3V of charge pumped gate drive DD pump to drive 4 external low-cost N-channel MOSFET Adjustable voltage slew rate for each rail switch gates above the IC bias voltage by 5.3V. These IC s Multiple sequencers can be easily daisy-chained to can be biased from and control any supply from 2.5V to 5V sequence an infinite number of independent voltages and additionally monitor any voltage above 0.7V. Individual product descriptions follow. Glitch immunity The four channel ISL8723 (ENABLE input), ISL8724 Undervoltage lockout for each monitored supply voltage (ENABLE input) offer the designer 4 voltage control when it 30A Sleep State (ISL8723) is required that all four rails are in minimal compliance prior Active high (ISL8723) or low (ISL8724) ENABLE input to turn on and that compliance must be maintained during operation. The ISL8723 has a low power standby mode Pb-free (RoHS compliant) when it is disabled suitable for battery powered applications. Applications External resistors provide flexible voltage threshold Graphics cards programming of monitored voltages. Delay and sequencing timing are programmable by external capacitors for both FPGA/ASIC/microprocessor/PowerPC supply sequencing ramp up and ramp down. Network Routers Ordering Information Telecommunications Systems TEMP. Pinout PART NUMBER PART RANGE PACKAGE PKG. (Note) MARKING (C) (Pb-free) DWG. ISL8723, ISL8724 (24 LD QFN) ISL8723IRZ* 87 23IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 TOP VIEW ISL8724IRZ* 87 24IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL8723EVAL1 Evaluation Platform *Add -T suffix for tape and reel. Please refer to TB347 for details on reel specifications. 24 23 22 21 20 19 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach ENABLE/ 1 18 DLY OFF A materials, and 100% matte tin plate plus anneal (e3 termination finish, ENABLE which is RoHS compliant and compatible with both SnPb and Pb-free GATE A 2 17 UVLO C soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free DLY OFF C 3 16 DLY ON C requirements of IPC/JEDEC J STD-020. 4mmx4mm 15 DLY OFF D 4 DLY ON D GATE B 5 14 UVLO D GATE C 6 13 DLY OFF B 7 8 9 10 11 12 FN6413 Rev 1.00 Page 1 of 14 April 22, 2009 GATE D RESET DLY ON B VDD NC SYSRST GND DLY ON A NC UVLO A UVLO B GNDISL8723, ISL8724 AIN AOUT VDD+5V BIAS VDD BIN BOUT LOCK OUT Q-PUMP CIN COUT 1A DIN DOUT 10A DLY ONX V DD UVLO A ENABLE UVLO B 1.26V -10A SYSRST 1A UVLO C RESET UVLO D GROUND DLY OFFX 10ms RISING DELAY 1.26V GATEX 30s FIGURE 1. TYPICAL ISL8723 APPLICATION FILTER USAGE UVLOX RESET LOGIC 0.633V 150ms RISING DELAY EN SYSRST FIGURE 2. ISL8723 BLOCK DIAGRAM (1/4) Pin Descriptions PIN PIN NAME FUNCTION DESCRIPTION 23 VDD Chip Bias Bias IC from nominal 2.5V to 5V 10, 19 GND Bias Return IC ground. NOTE: Pin 19 internally tied to GND with 6k. This pin can be tied to GND or left open. 1 ENABLE/ Input to start on/off Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is ENABLE sequencing disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE. 24 RESET RESET Output RESET provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization of output voltages. RESET will assert low upon any UVLO not being satisfied or ENABLE/ENABLE being deasserted. The RESET output is an open drain N-channel FET and is guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO X. 20 UVLO A Undervoltage Lock These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and Out/Monitoring are filtered to ignore short (<7s) transients below programmed UVLO level. 12 UVLO B Input 17 UVLO C 14 UVLO D 21 DLY ON A Gate On Delay Allows for programming the delay and sequence for V turn-on using a capacitor to ground. Each OUT Timer Output cap is charged with 1A, 10ms after turn-on initiated by ENABLE/ENABLE with an internal current 8DLY ON B source providing delayed enhancement of the associated FETs GATE to turn-on. 16 DLY ON C 15 DLY ON D FN6413 Rev 1.00 Page 2 of 14 April 22, 2009 DLY ON A GATE D DLY OFF A GATE C DLY ON B DLY OFF B DLY ON C GATE B DLY OFF C DLY ON D GATE A DLY OFF D DIN CIN BIN AIN