ISL88550AIRZ-T7 Renesas

DATASHEET ISL88550A FN6168 Rev 3.00 Synchronous Step-Down Controller with Sourcing and Sinking LDO Regulator April 23, 2008 ISL88550A integrates a synchronous buck PWM controller Features to generate VDDQ, a sourcing and sinking LDO linear Pb-Free (RoHS Compliant) regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller drives two Buck Controller external N-Channel MOSFETs to generate output voltages Constant-On PWM with 100ns Load-Step Response down to 0.7V from a 2V to 25V input with output currents up Start-up with Pre-biased Output Voltage to 15A. The LDO can source up to 2.5A and sink up to -2.0A continuously. Both the LDO output and the 10mA reference Up to 95% Efficiency buffer output can be made to track the REFIN voltage via a 2V to 25V Input Voltage Range built-in resistive divider. These features make the 2.5V Fixed or 0.7V to 3.5V Adjustable Output ISL88550A ideally suited for DDR memory applications in desktops, notebooks and graphics cards. 200kHz/300kHz/450kHz/600kHz Switching Frequencies Programmable Current Limit with Foldback Capability The PWM controller in the ISL88550A uses constant-on-time PWM architecture with a programmable switching frequency 1.7ms Digital Soft-Start and Independent Shutdown of up to 600kHz. This control scheme handles wide Overvoltage/Undervoltage Protection Option input/output voltage ratios with ease and provides 100ns instant-on response to load transients while maintaining Power-Good Window Comparator high efficiency and a relatively constant switching frequency. LDO Section The ISL88550A offers full programmable UVP/OVP and skip Fully Integrated VTT and VTTR Capability mode options ideal in portable applications. Skip mode allows for improved efficiency at lighter loads. VTT has +2.5A/-2.0A Sourcing/Sinking Capability Start-Up with Pre-Biased Output Voltage The VTT and VTTR outputs track to VREFIN/2. The high bandwidth of this LDO regulator allows excellent transient VTT and VTTR Outputs Track VREFIN/2 response without the need for bulk capacitors, thus reducing VTT and VTTR 1% of VREFIN/2 the cost and size. Low All-Ceramic Output Capacitor Designs The buck controller and LDO regulators are provided with 1.0V to 2.8V Input REFIN Range independent current limits. Adjustable loss-less fold-back current limit for the buck regulator is achieved by monitoring Analog Soft-Start Option and Independent Shutdown the drain-to-source voltage drop of the low side synchronous Power-Good Window Comparator MOSFET. Once overcurrent is removed, the regulator is allowed to enter soft-start again. This helps minimize power Applications dissipation during short-circuit condition. Additionally, DDR, DDR II and DDR III Memory Power Supplies overvoltage and undervoltage protection mechanisms are built in. The ISL88550A allow flexible sequencing and Desktop Computers standby power management using SHDNA , and STBY Notebooks and Desknotes inputs. Graphics Cards Game Consoles Networking and RAID Ordering Information PART NUMBER (Note) PART MARKING TEMP RANGE (C) PACKAGE (Pb-free) PKG. DWG. ISL88550AIRZ ISL88 550AIRZ -40 to +85 28 Ld 55 TQFN L28.5x5B ISL88550AIRZ-T* ISL88 550AIRZ -40 to +85 28 Ld 55 TQFN Tape and Reel L28.5x5B *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6168 Rev 3.00 Page 1 of 25 April 23, 2008ISL88550A Pinout ISL88550A (28 LD TQFN) TOP VIEW 28 27 26 25 24 23 22 TON 1 21 LGATE OVP/UVP 2 20 BOOT REF 3 19 PHASE 4 18 UGATE ILIM POK1 5 17 VIN 6 16 POK2 OUT 7 15 STBY FB 8 9 10 11 12 13 14 FN6168 Rev 3.00 Page 2 of 25 April 23, 2008 SS TP0 VTTS SHDNA VTTR AVDD PGND2 SKIP VTT GND VTTI PGND1 REFIN VDD