DATASHEET ISL89367 FN7727 Rev 1.00 High Speed, Dual Channel, 6A, MOSFET Driver With Programmable Rising and October 8, 2012 Falling Edge Delay Timers The ISL89367 is a high-speed, 6A, 2 channel MOSFET driver Features optimized for synchronous rectifier applications. Internal 2 outputs with 6A peak drive currents (sink and source) with timers can be programmed with resistors to delay the rising output voltage range of 4.5V to 16V and/or falling edges of the outputs. Logically ANDed dual inputs are also provided. One input is for the PWM signal and Typical ON-resistance <1 the second can be used as an enable. A third control input is Specified Miller plateau drive currents used to optionally invert the logical polarity of the driver EPAD provides very low thermal impedance ( = 3C/W) outputs. JC Dual logic inputs with hysteresis for high noise immunity Comparator like logical inputs allows this driver to be configured for any logic level from 3.3V to 10 VDC. The Rising and/or falling output edge delays programmed with precision logic thresholds provided by the comparators allow resistors the use of external RC circuits to generate longer time delays 20ns rise and fall time driving a 10nF load than are possible with the internal timers. The comparators Flexible logic options available by use of INVA and INVB pins also allow the driver to be configured with a low output voltage that is negative relative to the logic ground if desired. This is Applications useful for applications that require a negative turn-off gate drive voltage for driving FETs with logic thresholds. Synchronous Rectifier (SR) Driver Switch mode power supplies At high switching frequencies, these MOSFET drivers use very little bias current. Separate, non-overlapping drive circuits are Motor Drives, Class D amplifiers, UPS, Inverters used to drive each CMOS output FET to prevent shoot-thru Pulse Transformer Driver currents in the output stage. Clock/Line Driver The start-up sequence is design to prevent unexpected glitches when V is being turned on or turned off. When V < ~1V, DD DD Related Literature an internal 10k resistor between the output and ground helps to keep the output voltage low. When ~1V < V < UV, both AN1603 ISL6752/54EVAL1Z ZVS DC/DC Power Supply DD outputs are driven low with very low resistance and the logic with Synchronous Rectifiers User Guide inputs are ignored. This insures that the driven FETs are off. When V > UVLO, and after a short delay, the outputs now DD respond to the logic inputs. 350 300 3.3V +125C (WORST CASE) 250 VREF+ FDELA ENABLE INVA RDELA 200 12V /OUTA 150 +25C (TYPICAL) OUTB 100 GND PWM INVB RDELB 50 -40C (WORST CASE) FDELB VREF- 0 0 5 10 15 20 RDT (2k TO 20k) FIGURE 1. TYPICAL APPLICATION FIGURE 2. PROGRAMMABLE TIME DELAYS FN7727 Rev 1.00 Page 1 of 14 October 8, 2012 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc RISING OR FALLING EDGE DELAY (ns)ISL89367 Block Diagram VREF+ VDD For clarity, only one Separated gate drives channel is shown prevent shoot-thru currents in the output CMOS FETs. RDELx IN1x Rising edge Delay is delayed Timer The positive threshold is 63% of ((VREF+)-(VREF-)). OUTx The negative threshold is 37% of ((VREF+)-(VREF-)). Delay Timer Falling edge 10K is delayed INVx IN2x FDELx For proper thermal and VREF- VSS electrical performance, the EPAD must be connected to EPAD the PCB signal ground plane. FN7727 Rev 1.00 Page 2 of 14 October 8, 2012