DATASHEET ISL90842 FN8096 Rev 1.00 2 Quad Digitally Controlled Variable Resistors Low Noise, Low Power I C Bus, 256 Taps January 16, 2006 The ISL90842 integrates four digitally controlled Pinout potentiometers (DCP) configured as variable resistors on a ISL90842 monolithic CMOS integrated circuit. (14 LEAD TSSOP) TOP VIEW The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The RH3 1 14 RW0 position of the wipers are controlled by the user through the RW3 2 13 RH0 2 I C bus interface. Each potentiometer has an associated SCL 3 12 VCC Wiper Register (WR) that can be directly written to and read SDA 4 11 A1 by the user. The contents of the WR controls the position of GND 5 10 A0 the wiper. RW2 6 9 RH1 The DCPs can be used as two-terminal variable resistors in RH2 7 8 RW1 a wide variety of applications including control, parameter adjustments, and signal processing. Features Four variable resistors in one package 256 resistor taps - 0.4% resolution 2 I C serial interface Wiper resistance: 70 typical 3.3V Standby current <5A max Power supply: 2.7V to 5.5V 50k , 10k total resistance 14 Lead TSSOP Pb-free plus anneal available (RoHS compliant) Ordering Information RESISTANCE OPTION TEMP RANGE PART NUMBER PART MARKING () (C) PACKAGE ISL90842UIV1427Z (Notes 1 & 2) 90842UI27Z 50K -40 to +85 14 Ld TSSOP (Pb-Free) ISL90842WIV1427Z (Notes 1 & 2) 90842WI27Z 10K -40 to +85 14 Ld TSSOP (Pb-Free) NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add -TK suffix for Tape and Reel. FN8096 Rev 1.00 Page 1 of 10 January 16, 2006ISL90842 Functional Diagram V R R R R CC H0 H1 H2 H3 SCL SDA 2 I C INTERFACE A0 A1 R R R R L L L L GND R R R R W0 W1 W2 W3 Block Diagram V CC R H3 WR3 DCP3 R W3 * R H2 2 WR2 DCP2 R I C INTERFACE POWER-UP, W2 SDA * INTERFACE, CONTROL AND STATUS SCL R H1 LOGIC WR1 DCP1 R W1 * A1 R H0 A0 WR0 DCP0 R W0 * GND * THE R PINS OF EACH DCP ARE LEFT FLOATING L Pin Descriptions TSSOP PIN SYMBOL DESCRIPTION 1 RH3 High terminal of DCP3 2 RW3 Wiper terminal of DCP3 2 3SCLI C interface clock 2 4 SDA Serial data I/O for the I C interface 5 GND Device ground pin 6 RW2 Wiper terminal of DCP2 7 RH2 High terminal of DCP2 8 RW1 Wiper terminal of DCP1 9 RH1 High terminal of DCP1 2 10 A0 Device address for the I C interface 2 11 A1 Device address for the I C interface 12 VCC Power supply pin 13 RH0 High terminal of DCP0 14 RW0 Wiper terminal of DCP0 FN8096 Rev 1.00 Page 2 of 10 January 16, 2006