ISL94208IRZ Renesas

DATASHEET ISL94208 FN8306 Rev.2.00 4- to 6-Cell Li-ion Battery Management Analog Front-End May 1, 2017 The ISL94208 battery management IC is designed for use with a Features microcontroller and features an analog front-end with Software selectable overcurrent protection levels and variable overcurrent protection for multi-cell Li-ion battery packs. The protect detection times ISL94208 supports battery packs consisting of four to six cells in series and one or more cells in parallel. - 4 discharge overcurrent thresholds - 4 short-circuit thresholds Using an internal analog multiplexer, the ISL94208 allows a separate microcontroller with an A/D converter to monitor each - 4 charge overcurrent thresholds cell voltage plus internal and external temperature. - 8 overcurrent delay times (charge) - 8 overcurrent delay times (discharge) The ISL94208 provides integral overcurrent and short-circuit protection circuitry, an internal 3.3V voltage regulator, internal - 2 short-circuit delay times (discharge) cell balancing switches, and drive circuitry for external FET Automatic FET turn-off and cell balance disable on reaching devices for control of pack charge and discharge. external (battery) or internal (IC) temperature limit Automatic cell balance turn off on IC over-temperature Related Literature Integrated charge/discharge FET drive circuitry For a full list of related documents, visit our website - ISL94208 product page Internal cell balancing FETs handle up to 200mA of balancing current for each cell Sleep operation with negative or positive edge wake-up <10A Sleep mode Applications Power tools Portable equipment Battery backup systems Military electronics P+ ISL94208 VBACK VCC WKUP VCELL6 CB6 VCELL5 RGC CB5 RGO VCELL4 C CB4 SCL SCL V VFET2 CC SDA SDA VCELL3 TEMPI CB3 RESET TEMP3V VFET1 INT CHRG VCELL2 AO A/D INPUT CB2 I/O VMON VBACK CFET VCELL1 CB1 DFET VCELL0 B- V SS P- FIGURE 1. TYPICAL APPLICATION FN8306 Rev.2.00 Page 1 of 36 May 1, 2017 THERM ISREF CSENSE DSENSEISL94208 Table of Contents Ordering Information 3 Key Differences Between Family of Parts . 3 Pin Configuration 3 Pin Descriptions . 4 Block Diagram 5 Absolute Maximum Ratings . 6 Thermal Information . 6 Recommended Operating Conditions 6 Electrical Specifications . 6 Timing Diagrams . 12 Registers 15 Status Registers . 16 Control Registers 17 Configuration Registers . 18 Device Description . 21 Battery Connection . 21 System Power-Up/Power-Down . 21 WKUP Pin Operation 22 Protection Functions 24 Overcurrent Safety Functions 24 Load Monitoring . 25 Over-Temperature Safety Functions 25 Analog Multiplexer Selection . 26 Voltage Monitoring 26 Temperature Monitoring 26 Cell Balancing 27 Overview . 27 Definition of Cell Balancing . 27 Cell Balance Operation . 27 External VMON/CFET Protection Mechanisms 27 User Flags . 28 2 I C Interface . 28 Interface Conventions 28 Clock and Data 28 Start Condition 28 Stop Condition 28 Write Operations 30 Read Sequence 30 Register Protection 31 Operation State Machine . 31 Application Circuits . 32 Integrated Charge/Discharge Path . 32 Separate Charge/Discharge Path 33 PC Board Layout 34 QFN Package . 34 Alternate VFET Power Supply 34 Revision History 35 About Intersil 35 Package Outline Drawing 36 FN8306 Rev.2.00 Page 2 of 36 May 1, 2017