DATASHEET ISLA110P50 FN7606 Rev 2.00 10-Bit, 500MSPS A/D Converter July 25, 2011 The ISLA110P50 is a low-power, high-performance, 500MSPS Features analog-to-digital converter designed with Intersils proprietary 1.15GHz Analog Input Bandwidth FemtoCharge technology on a standard CMOS process. The ISLA110P50 is part of a pin-compatible portfolio of 8, 10 and 90fs Clock Jitter 12-bit A/Ds. This device is an upgrade of the KAD551XP-50 Automatic Fine Interleave Correction Calibration product family and is pin similar. Multiple Chip Time Alignment Support via the Synchronous The device utilizes two time-interleaved 250MSPS unit A/Ds to Clock Divider Reset achieve the ultimate sample rate of 500MSPS. A single Programmable Gain, Offset and Skew Control 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Over-Range Indicator Intersil Interleave Engine (I2E) performs automatic fine Clock Phase Selection correction of offset, gain, and sample time skew mismatches Nap and Sleep Modes between the unit A/Ds to optimize performance. No external interleaving algorithm is required. Twos Complement, Gray Code or Binary Data Format A serial peripheral interface (SPI) port allows for extensive DDR LVDS-Compatible or LVCMOS Outputs configurability of the A/D. The SPI also controls the interleave Programmable Test Patterns and Internal Temperature correction circuitry, allowing the system to issue continuous Sensor calibration commands as well as configure many dynamic parameters. Applications Digital output data is presented in selectable LVDS or CMOS Radar and Electronic/Signal Intelligence formats. The ISLA110P50 is available in a 72 Ld QFN package Broadband Communications with an exposed paddle. Performance is specified over the full High-Performance Data Acquisition industrial temperature range (-40C to +85C). Pin-Compatible Family SPEED MODEL RESOLUTION (MSPS) ISLA112P50 12 500 CLKP CLKOUTP CLOCK ISLA110P50 10 500 MANAGEMENT CLKN CLKOUTN ISLA118P50 8 500 Key Specifications 10- BIT D 9:0 P SHA 250MSPS ADC SNR = 60.6dBFS for f = 190MHz (-1dBFS) D 9:0 N IN VREF ORP SFDR = 80dBc for f = 190MHz (-1dBFS) IN DIGITAL VINP ORN Gain/ Offset/Skew Total Power Consumption = 441mW I2E ERROR Adjustments VINN CORRECTION OUTFMT OUTMODE 10-BIT VCM SHA 250MSPS ADC VREF + 1.25V SPI CONTROL FIGURE 1. BLOCK DIAGRAM FN7606 Rev 2.00 Page 1 of 34 July 25, 2011 NAPSLP AGND AVDD CLKDIVRSTP RESETN CLKDIVRSTN CSB SCLK SDIO SDO OGND OVDDISLA110P50 Table of Contents Ordering Information 3 Clock Divider Synchronous Reset 20 Pin Configuration 3 Serial Peripheral Interface 22 Pin Descriptions . 4 SPI Physical Interface . 22 SPI Configuration . 23 Absolute Maximum Ratings . 5 Device Information 23 Thermal Information . 5 Indexed Device Configuration/Control 23 AC RMS Power Threshold 25 Digital Specifications 7 Address 0x60-0x64: I2E initialization 25 Device Test 26 Timing Diagrams 8 SPI Memory Map . 28 Switching Specifications . 9 Equivalent Circuits . 30 Typical Performance Curves .10 A/D Evaluation Platform 31 Theory of Operation .14 Layout Considerations 31 Functional Description . 14 Split Ground and Power Planes . 31 Power-On Calibration . 14 Clock Input Considerations . 31 User Initiated Reset 15 Exposed Paddle . 31 Analog Input 15 Bypass and Filtering . 31 Clock Input . 16 LVDS Outputs 31 Jitter . 16 LVCMOS Outputs 31 Voltage Reference . 17 Unused Inputs 31 Digital Outputs 17 Over-Range Indicator . 17 Definitions 31 Power Dissipation . 17 Nap/Sleep 17 Revision History . 33 Data Format 17 Products 33 I2E Requirements and Restrictions . 18 Package Outline Drawing . 34 Overview .18 Active Run State 18 Power Meter 19 Notch Filter . 19 Nyquist Zones . 19 Configurability and Communication 19 FN7606 Rev 2.00 Page 2 of 34 July 25, 2011