DATASHEET ISLA112P50 FN7604 Rev.3.0 12-Bit, 500MSPS A/D Converter Jul 6, 2021 The ISLA112P50 is a low-power, high-performance, 500MSPS Features analog-to-digital converter designed with Renesas proprietary 1.15GHz Analog Input Bandwidth FemtoCharge technology on a standard CMOS process. The ISLA112P50 is part of a pin-compatible portfolio of 8, 10 and 90fs Clock Jitter 12-bit A/Ds. This device an upgrade of the KAD551XP-50 Automatic Fine Interleave Correction Calibration product family and is pin similar. Multiple Chip Time Alignment Support via the Synchronous The device utilizes two time-interleaved 250MSPS unit A/Ds to Clock Divider Reset achieve the ultimate sample rate of 500MSPS. A single Programmable Gain, Offset and Skew Control 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Over-Range Indicator Interleave Engine (I2E) performs automatic fine correction of Clock Phase Selection offset, gain, and sample time skew mismatches between the Nap and Sleep Modes unit A/Ds to optimize performance. No external interleaving algorithm is required. Twos Complement, Gray Code or Binary Data Format A serial peripheral interface (SPI) port allows for extensive DDR LVDS-Compatible or LVCMOS Outputs configurability of the A/D. The SPI also controls the interleave Programmable Test Patterns and Internal Temperature correction circuitry, allowing the system to issue continuous Sensor calibration commands as well as configure many dynamic parameters. Applications Digital output data is presented in selectable LVDS or CMOS Radar and Electronic/Signal Intelligence formats. The ISLA112P50 is available in a 72 Ld QFN package with an exposed paddle. Performance is specified over the full Broadband Communications industrial temperature range (-40C to +85C). High-Performance Data Acquisition TABLE 1. PIN-COMPATIBLE FAMILY SPEED MODEL RESOLUTION (MSPS) ISLA112P50 12 500 CLKP CLKOUTP ISLA110P50 10 500 CLOCK MANAGEMENT CLKN ISLA118P50 8 500 CLKOUTN Key Specifications 12 - BIT SNR = 65.8dBFS for f = 190MHz (-1dBFS) IN D 11:0 P SHA 250 MSPS ADC D 11:0 N SFDR = 80dBc for f = 190MHz (-1dBFS) IN VREF ORP Total Power Consumption = 455mW DIGITAL VINP ORN ERROR Gain/Offset/Skew I2 E Adjustments VINN CORRECTION OUTFMT OUTMODE 12 -BIT VCM SHA 250 MSPS ADC VREF + 1.25V SPI CONTROL FIGURE 1. BLOCK DIAGRAM FN7604 Rev.3.0 Page 1 of 33 Jul 6, 2021 2010 Renesas Electronics NAPSLP AGND AVDD CLKDIVRSTP RESET N CLKDIVRSTN CSB SCLK SDIO SDO OGND OVDDISLA112P50 Table of Contents Pin Descriptions . 4 Definitions 31 Absolute Maximum Ratings . 5 Revision History . 32 Thermal Information . 5 Package Outline Drawing . 33 Recommended Operating Conditions 5 Electrical Specifications . 5 Digital Specifications 7 Timing Diagrams 8 Switching Specifications . 9 Typical Performance Curves .10 Theory of Operation .14 Functional Description . 14 Power-On Calibration . 14 User Initiated Reset 15 Analog Input 15 Clock Input . 16 Jitter . 16 Voltage Reference . 16 Digital Outputs 17 Over-Range Indicator . 17 Power Dissipation . 17 Nap/Sleep 17 Data Format 17 I2E Requirements and Restrictions .18 Overview .18 Active Run State 18 Power Meter 19 Notch Filter . 19 Nyquist Zones . 19 Configurability and Communication 19 Clock Divider Synchronous Reset .20 Serial Peripheral Interface 22 SPI Physical Interface 22 SPI Configuration 23 Device Information 23 Indexed Device Configuration/Control 23 AC RMS Power Threshold . 25 Address 0x60-0x64: I2E initialization . 25 Device Test . 26 SPI Memory Map 28 Equivalent Circuits .30 A/D Evaluation Platform .31 Layout Considerations 31 Split Ground and Power Planes 31 Clock Input Considerations 31 Exposed Paddle . 31 Bypass and Filtering . 31 LVDS Outputs . 31 LVCMOS Outputs 31 Unused Inputs 31 FN7604 Rev.3.0 Page 2 of 33 Jul 6, 2021