ISLA216S25IR48EV1Z Renesas

DATASHEET ISLA216S FN7996 Rev 1.00 16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC April 19, 2013 The ISLA216S is a series of low-power, high-performance, Features 16-bit, analog-to-digital converters. Designed with JESD204A/B High Speed Data Interface FemtoCharge technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The -JESD204A Compliant ISLA216S is part of a pin-compatible family of 12-, 14-, and - JESD204B Device Subclass 0 Compliant 16-bit A/Ds with maximum sample rates ranging from 130 to - JESD204B Device Subclass 2 Compatible 500MSPS and shares the same analog core as Intersil s - JESD204 Output Lanes Run up to 4.375Gbps proven ISLA216P series of ADCs. The family minimizes power - Highly Configurable JESD204 Transmitter consumption while providing state-of-the art dynamic performance, offering an optimal performance-vs-power Multiple Chip Time Alignment and Deterministic Latency trade-off. Support (JESD204B Device Subclass 2) Differentiating the ISLA216S from the ISLA216P is its highly SPI Programmable Debugging Features and Test Patterns configurable, JESD204B-compliant, high speed serial output 48-pin QFN 7mmx7mm Package link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It uses two lanes to transmit the Key Specifications conversion data. The SERDES transmitter also provides SNR 250/200/130MSPS deterministic latency and multi-chip time alignment support to 75.8/77.2/78.0 dBFS f = 30MHz IN satisfy an application s complex synchronization requirements. 74.6/75.2/74.8 dBFS f = 190MHz IN A serial peripheral interface (SPI) port allows for extensive SFDR 250/200/130MSPS configurability of the JESD204B transmitter including access to its built-in link and transport-layer test patterns. The SPI port 87/93/94 dBc f = 30MHz IN also provides control for numerous additional features 82/81/81 dBc f = 190MHz IN including the fine gain and offset adjustments of the two ADC cores as well as the programmable clock divider, enabling 2x Total Power Consumption: 887mW 250MSPS and 4x harmonic clocking. Applications The ISLA216S is available in a space-saving 7mmx7mm 48 Ld Radar and Satellite Antenna Array Processing QFN package. The package features a thermal pad for improved thermal performance and is specified over the full Broadband Communications and Microwave Receivers industrial temperature range (-40C to +85C). High-Performance Data Acquisition Communications Test Equipment High-Speed Medical Imaging Pin-Compatible Family SPEED PRODUCT MODEL RESOLUTION (MSPS) AVAILABILITY ISLA216S25 16 250 Now ISLA216S20 16 200 Now ISLA216S13 16 130 Now ISLA214S50 14 500 Now ISLA212S50 12 500 Soon ISLA214S25 14 250 Soon ISLA212S25 12 250 Soon FIGURE 1. SERDES DATA EYE AT 4.375Gbps FN7996 Rev 1.00 Page 1 of 34 April 19, 2013ISLA216S CLKP CLOCK GENERATION CLKN LANE 1:0 P VINP 16-BIT LANE 1:0 N JESD204 SHA 250MSPS TRANSMITTER VINN ADC VREF + 1.25V VCM SPI CONTROL FIGURE 2. BLOCK DIAGRAM Pin Configuration ISLA216S (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VCM 1 36 OVDD AVDD 2 35 OVSS DNC AVSS 3 34 AVSS DNC 4 33 VINN 5 32 OVSS VINN 6 31 LANE1N LANE1P VINP 7 30 VINP 8 29 OVSS LANE0N AVSS 9 28 LANE0P AVSS 10 27 AVDD 11 26 OVSS PAD Exposed Paddle DNC 12 25 OVDD 13 14 15 16 17 18 19 20 21 22 23 24 FN7996 Rev 1.00 Page 2 of 34 April 19, 2013 RESETN DNC AVDD DNC AVDD AVDD NAPSLP NAPSLP CLKP AVSS AVDD CLKN CLKDIV AVSS (PLL) SYNCP SDIO SYNC SYNCN SCLK CSB RESETN DNC OVSS (PLL) SDO CSB SCLK SDIO OVDD (PLL) OVDD OVDD SDO (PLL) OVSS OVSS OVDD OVSS (PLL) OVSS OVDD (PLL)