Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC ISLA224P Features The ISLA224P is a family of dual-channel 14-Bit analog-to-digital Single supply 1.8V operation converters. Designed with Intersils proprietary FemtoCharge Clock duty cycle stabilizer technology on a standard CMOS process, the family supports 75fs clock jitter sampling rates of up to 250MSPS. The ISLA224P is part of a pin-compatible portfolio of 12-bit and 14-bit dual-channel A/Ds 700MHz bandwidth with maximum sample rates ranging from 130MSPS to Programmable built-in test patterns 250MSPS. Multi-ADC support A serial peripheral interface (SPI) port allows for extensive - SPI programmable fine gain and offset control configurability, as well as fine control of various parameters such - Support for multiple ADC synchronization as gain and offset. - Optimized output timing Digital output data is presented in selectable LVDS or CMOS Nap and sleep modes formats. The ISLA224P is available in a 72-contact QFN package - 200s sleep wake-up time with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature Data output clock range (-40C to +85C). DDR LVDS-compatible or LVCMOS outputs Selectable clock divider Key Specifications SNR 250/200/130MSPS Applications 72.7/73.9/74.7dBFS f = 30MHz IN Radar array processing 70.2/70.7/70.2dBFS f = 363MHz IN Software defined radios SFDR 250/200/130MSPS Broadband communications 84/86/86dBc f = 30MHz IN 73/75/79dBc f = 363MHz High-performance data acquisition IN Total Power Consumption = 837mW 250MSPS Communications test equipment Pin-Compatible Family SPEED MODEL RESOLUTION (MSPS) ISLA224P25 14 250 CLKP CLKOUTP CLOCK MANAGEMENT ISLA224P20 14 200 CLKN CLKOUTN ISLA224P13 14 130 14-BIT VINBP D 13:0 P ISLA222P25 12 250 SHA 250 MSPS VINBN ADC D 13:0 N ISLA222P20 12 200 ORP VREF DIGITAL ORN ERROR VCM ISLA222P13 12 130 CORRECTION OUTFMT OUTMODE VINAN 14-BIT SHA 250 MSPS VINAP ADC VREF SPI + + 1.25V - CONTROL November 30, 2012 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved FN7570.1 Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. AVSS AVDD NAPSLP RESETN CLKDIV CLKDIVRSTP CLKDIVRSTN CSB SCLK SDIO SDO OVSS OVDDISLA224P Pin Configuration - LVDS Mode ISLA224P (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DNC 1 54 D3P D3N DNC 2 53 NAPSLP 3 52 D4P 4 51 VCM D4N 5 50 AVSS D5P 6 49 VINBP D5N VINBN 7 48 CLKOUTP 8 47 AVSS CLKOUTN 9 46 AVDD RLVDS 10 45 AVDD OVSS 11 44 AVSS D6P 12 43 VINAN D6N 13 42 VINAP D7P 14 41 AVSS D7N CLKDIV 15 40 D8P IPTAT 16 39 D8N Thermal Pad Not Drawn to Scale. 17 38 DNC Consult Mechanical Drawing for D9P Connect Thermal Pad to AVSS Physical Dimensions. RESETN 18 37 D9N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Descriptions - 72 Ld QFN, LVDS Mode PIN NUMBER LVDS PIN NAME LVDS PIN FUNCTION 1, 2, 17 DNC Do Not Connect 9, 10, 19, 20, 21, 70, 71, 72 AVDD 1.8V Analog Supply 5, 8, 11, 14 AVSS Analog Ground 27, 32, 62 OVDD 1.8V Output Supply 26, 45, 61, 65 OVSS Output Ground 3 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 4 VCM Common Mode Output 6, 7 VINBP, VINBN Channel B Analog Input Positive, Negative FN7570.1 2 November 30, 2012 AVDD AVDD AVDD AVDD AVDD AVDD CLKP SDIO CLKN SCLK CLKDIVRSTP CSB CLKDIVRSTN SDO OVSS OVSS OVDD ORP D13N ORN D13P OVDD D12N OVSS D12P D0P OVDD D0N D11N D1P D11P D1N D10N D2P D10P D2N