M10042040054X0PWAR Renesas

High Performance M1004204/M1008204/M1016204 Serial MRAM Memory M3004204/M3008204/M3016204 Description Features Mxxxx204 is a magneto-resistive random-access memory Interface (MRAM). It is offered in density ranging from 4Mbit to 16Mbit. Serial Peripheral Interface QSPI (4-4-4) MRAM technology is analogous to Flash technology with SRAM Single Data Rate Mode: 108MHz compatible read/write timings (Persistent SRAM, P-SRAM). Data is Double Data Rate Mode: 54MHz always non-volatile. Technology 40nm pMTJ STT-MRAM MRAM is a true random-access memory allowing both reads and writes to occur randomly in memory. MRAM is ideal for applications Virtually unlimited Endurance and Data Retention (see that must store and retrieve data without incurring large latency Endurance and Data Retention specification on page 38) penalties. It offers low latency, low power, virtually infinite Density endurance and retention, and scalable non-volatile memory 4Mb, 8Mb, 16Mb technology. Operating Voltage Range VCC: 1.71V 2.00V Mxxxx204 is available in small footprint 8-pad DFN (WSON) and 8- VCC: 2.70V 3.60V pin SOIC packages. These packages are compatible with similar low-power volatile and non-volatile products. Operating Temperature Range Industrial: -40C to 85C Mxxxx204 is offered with industrial (-40C to 85C) and industrial Industrial Plus: -40C to 105C plus (-40C to 105C) operating temperature ranges. Packages 8-pad DFN (WSON) (5.0mm x 6.0mm) 8-pin SOIC (5.2mm x 5.2mm) Typical Applications Data Protection Ideal for applications that must store and retrieve data Hardware Based: Write Protect Pin (WP ) without incurring large latency penalties. Software Based: Address Range Selectable through Configuration bits (Top/Bottom, Block Protect 2:0 ) Factory Automation Identification Multifunction Printers 64-bit Unique ID Industrial Control And Monitoring 64-bit User Programmable Serial Number Medical Diagnostics Augmented Storage Array Data Switches And Routers 256-byte User Programmable with Write Protection Supports JEDEC Reset RoHS Compliant Block Diagram CS V Address Register CC Status Register Serial I/Os Column Decoder Command Register SO / IO 1 IO 3 MRAM MRAM MRAM Array WP / IO 2 Array CLK Command Array & Control High Voltage Generator V SI / IO 0 SS Regulator Data Buffer Feb.25.21 Page 1 Row Decoder M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Contents 1. Performance ............................................................................................................................................................................................3 2. General Description ...............................................................................................................................................................................3 3. Ordering Options ....................................................................................................................................................................................4 3.1 Valid Combinations Standard .........................................................................................................................................................4 4. Signal Description and Assignment ..................................................................................................................................................7 5. Package Options ....................................................................................................................................................................................9 5.1 8-Pad DFN (WSON) (Top View) ..........................................................................................................................................................9 5.2 8-Pin SOIC (Top View) ........................................................................................................................................................................9 6. Package Drawings ...............................................................................................................................................................................10 6.1 8-Pad DFN (WSON) ..........................................................................................................................................................................10 6.2 8-Pin SOIC ........................................................................................................................................................................................11 7. Architecture ............................................................................................................................................................................................12 8. Device Initialization ..............................................................................................................................................................................14 9. Memory Map ..........................................................................................................................................................................................16 10. Augmented Storage Array Map .......................................................................................................................................................16 11. Register Addresses .............................................................................................................................................................................16 12. Register Map..........................................................................................................................................................................................17 12.1 Status Register / Device Protection Register (Read/Write) ...............................................................................................................17 12.2 Augmented Storage Array Protection Register (Read/Write) ............................................................................................................18 12.3 Device Identification Register (Read Only) ........................................................................................................................................19 12.4 Serial Number Register (Read/Write) ................................................................................................................................................19 12.5 Unique Identification Register (Read Only) .......................................................................................................................................19 12.6 Configuration Register 1 (Read/Write)...............................................................................................................................................20 12.7 Configuration Register 2 (Read/Write)...............................................................................................................................................21 12.8 Configuration Register 3 (Read/Write)...............................................................................................................................................23 12.9 Configuration Register 4 (Read/Write)...............................................................................................................................................23 13. Instruction Set ........................................................................................................................................................................................24 14. Instruction Description and Structures ...........................................................................................................................................27 15. Electrical Specifications ......................................................................................................................................................................38 15.1 CS Operation & Timing ....................................................................................................................................................................42 15.2 Data Output Operation & Timing .......................................................................................................................................................44 15.3 WP Operation & Timing ...................................................................................................................................................................45 Enter Deep Power Down Command (EDP B9h) ............................................................................................................................46 Exit Deep Power Down Command (EXDPD - ABh) ..........................................................................................................................47 Enter Hibernate Command (EHBN BAh) ........................................................................................................................................48 16. Thermal Resistance .............................................................................................................................................................................49 17. Revision History ....................................................................................................................................................................................50 Feb.25.21 Page 2