Datasheet R01DS0053EJ0330 RL78/G14 Rev. 3.30 RENESAS MCU Aug 12, 2016 True Low Power Platform (as low as 66 A/MHz, and 0.60 A for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 512 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-Low Power Consumption Technology Event Link Controller (ELC) VDD = single power supply voltage of 1.6 to 5.5 V which Event signals of 19 to 26 types can be linked to the specified peripheral function. can operate a 1.8 V device at a low voltage HALT mode Serial Interfaces STOP mode CSI: 3 to 8 channels SNOOZE mode UART/UART (LIN-bus supported): 3 or 4 channels 2 2 RL78 CPU Core I C/simplified I C: 3 to 8 channels CISC architecture with 3-stage pipeline Timer Minimum instruction execution time: Can be changed 16-bit timer: 8 to 12 channels from high speed (0.03125 s: 32 MHz operation with (Timer Array Unit (TAU): 4 to 8 channels, Timer RJ: 1 high-speed on-chip oscillator) to ultra-low speed (30.5 channel, Timer RD: 2 channels, Timer RG: 1 channel) s: 32.768 kHz operation with subsystem clock) 12-bit interval timer: 1 channel Multiply/divide/multiply & accumulate instructions are Real-time clock: 1 channel (calendar for 99 years, alarm supported. function, and clock correction function) Address space: 1 MB Watchdog timer: 1 channel (operable with the dedicated General-purpose registers: (8-bit register 8) 4 banks low-speed on-chip oscillator) On-chip RAM: 2.5 to 48 KB A/D Converter Code Flash Memory 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V) Code flash memory: 16 to 512 KB Analog input: 8 to 20 channels Block size: 1 KB Internal reference voltage (1.45 V) and temperature Prohibition of block erase and rewriting (security sensor function) On-chip debug function D/A Converter 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V) Self-programming (with boot swap function/flash shield Analog output: None or up to two channels window function) Output voltage: 0 V to VDD Data Flash Memory Real-time output function Data flash memory: 4 KB and 8 KB Comparator Back ground operation (BGO): Instructions can be None or up to two channels executed from the program memory while rewriting the Operating modes: Comparator high-speed mode, data flash memory. comparator low-speed mode, window mode Number of rewrites: 1,000,000 times (TYP.) The external reference voltage or internal reference Voltage of rewrites: VDD = 1.8 to 5.5 V voltage can be selected as the reference voltage. High-speed On-chip Oscillator I/O Port Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz, I/O port: 26 to 92 (N-ch open drain I/O withstand 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and voltage of 6 V : 2 to 4, N-ch open drain I/O VDD 1 MHz withstand voltage/EVDD withstand voltage : 10 to 28) High accuracy: 1.0% (VDD = 1.8 to 5.5 V, TA = -20 to Can be set to N-ch open drain, TTL input buffer, and on- +85C chip pull-up resistor Operating Ambient Temperature Different potential interface: Can connect to a 1.8/2.5/3 TA = -40 to +85C (A: Consumer applications, D: V device Industrial applications) On-chip key interrupt function TA = -40 to +105C (G: Industrial applications) On-chip clock output/buzzer output controller Power Management and Reset Function Others On-chip power-on-reset (POR) circuit On-chip BCD (binary-coded decimal) correction circuit On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels) Remark The functions mounted depend on the product. See 1.6 Outline of Functions. Data Transfer Controller (DTC) Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode Activation sources: Activated by interrupt sources. Chain transfer function R01DS0053EJ0330 Rev. 3.30 Page 1 of 208 Aug 12, 2016RL78/G14 1. OUTLINE ROM, RAM capacities RL78/G14 Flash ROM Data flash RAM 30 pins 32 pins 36 pins 40 pins 192 KB 8 KB 20 KB R5F104EH 128 KB 8 KB 16 KB R5F104AG R5F104BG R5F104CG R5F104EG 96 KB 8 KB 12 KB R5F104AF R5F104BF R5F104CF R5F104EF Note 64 KB 4 KB 5.5 KB R5F104AE R5F104BE R5F104CE R5F104EE Note 48 KB 4 KB 5.5 KB R5F104AD R5F104BD R5F104CD R5F104ED 32 KB 4 KB 4 KB R5F104AC R5F104BC R5F104CC R5F104EC 16 KB 4 KB 2.5 KB R5F104AA R5F104BA R5F104CA R5F104EA RL78/G14 Flash ROM Data flash RAM 44 pins 48 pins 52 pins 64 pins Note 512 KB 8 KB 48 KB R5F104GL R5F104LL 384 KB 8 KB 32 KB R5F104GK R5F104LK Note 256 KB 8 KB 24 KB R5F104FJ R5F104GJ R5F104JJ R5F104LJ 192 KB 8 KB 20 KB R5F104FH R5F104GH R5F104JH R5F104LH 128 KB 8 KB 16 KB R5F104FG R5F104GG R5F104JG R5F104LG 96 KB 8 KB 12 KB R5F104FF R5F104GF R5F104JF R5F104LF Note 64 KB 4 KB 5.5 KB R5F104FE R5F104GE R5F104JE R5F104LE Note 48 KB 4 KB 5.5 KB R5F104FD R5F104GD R5F104JD R5F104LD 32 KB 4 KB 4 KB R5F104FC R5F104GC R5F104JC R5F104LC 16 KB 4 KB 2.5 KB R5F104FA R5F104GA RL78/G14 Flash ROM Data flash RAM 80 pins 100 pins Note 512 KB 8 KB 48 KB R5F104ML R5F104PL 384 KB 8 KB 32 KB R5F104MK R5F104PK Note 256 KB 8 KB 24 KB R5F104MJ R5F104PJ 192 KB 8 KB 20 KB R5F104MH R5F104PH 128 KB 8 KB 16 KB R5F104MG R5F104PG 96 KB 8 KB 12 KB R5F104MF R5F104PF The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F104xD (x = A to C, E to G, J, L): Start address FE900H R5F104xE (x = A to C, E to G, J, L): Start address FE900H R5F104xJ (x = F, G, J, L, M, P): Start address F9F00H R5F104xL (x = G, L, M, P): Start address F3F00H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0053EJ0330 Rev. 3.30 Page 2 of 208 Aug 12, 2016