Preliminary Datasheet Specifications in this document are tentative and subject to change. RL78/G1A R01DS0151EJ0001 Rev.0.01 RENESAS MCU 2011.12.26 Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 A/MHz, and 0.57 A for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz 1. OUTLINE 1.1 Features Ultra-Low Power Technology Data Memory Access (DMA) Controller 1.6 V to 3.6 V operation from a single supply Up to 2 fully programmable channels Stop (RAM retained): 0.23 A, (LVD enabled): 0.31 Transfer unit: 8- or 16-bit A Halt (RTC + LVD): 0.57 A Multiple Communication Interfaces 2 Snooze: T.B.D. Up to 6 x I C master 2 Operating: 66 A/MHz Up to 1 x I C multi-master Up to 6 x CSI/SPI (7-, 8-bit) 16-bit RL78 CPU Core Up to 3 x UART (7-, 8-, 9-bit) Delivers 41 DMIPS at maximum operating frequency Up to 1 x LIN of 32 MHz Instruction Execution: 86% of instructions can be Extended-Function Timers executed in 1 to 2 clock cycles Multi-function 16-bit timers: Up to 8 channels CISC Architecture (Harvard) with 3-stage pipeline Real-time clock (RTC): 1 channel (full calendar and Multiply Signed & Unsigned: 16 x 16 to 32-bit result in alarm function with watch correction function) 1 clock cycle Interval Timer: 12-bit, 1 channel MAC: 16 x 16 to 32-bit result in 2 clock cycles 15 kHz watchdog timer: 1 channel (window function) 16-bit barrel shifter for shift & rotate in 1 clock cycle 1-wire on-chip debug function Rich Analog ADC: Up to 28 channels, 12-bit resolution, 3.375 s Code Flash Memory conversion time Density: 16 KB to 64 KB Supports 1.6 V Block size: 1 KB Internal voltage reference (1.45 V) On-chip single voltage flash memory with protection On-chip temperature sensor from block erase/writing Self-programming with secure boot swap function Safety Features (IEC or UL 60730 compliance) and flash shield window function Flash memory CRC calculation RAM parity error check Data Flash Memory RAM write protection Data Flash with background operation SFR write protection Data flash size: 4 KB Illegal memory access detection Erase Cycles: 1 Million (typ.) Clock stop/ frequency detection Erase/programming voltage: 1.8 V to 3.6 V ADC self-test RAM General Purpose I/O 2 KB to 4 KB size options 3.6 V tolerant, high-current (up to 20 mA per pin) Supports operands or instructions Open-Drain, Internal Pull-up support Back-up retention in all modes Operating Ambient Temperature High-speed On-chip Oscillator Standard: 40 C to +85 C 32 MHz with +/ 1% accuracy over voltage (1.8 V to 3.6 V) and temperature (20 C to +85 C) Package Type and Pin Count Pre-configured settings: 32 MHz, 24 MHz, 16 MHz, From 3 mm x 3 mm to 10 mm x 10 mm 12 MHz, 8 MHz, 4 MHz & 1 MHz QFP: 48, 64 QFN: 32, 48 Reset and Supply Management LGA: 25 Power-on reset (POR) monitor/generator BGA: 64 Low voltage detection (LVD) with 12 setting options (Interrupt and/or reset function) R01DS0151EJ0001 Rev.0.01 Page 1 of 76 2011.12.26 Preliminary document Under development Specifications in this document are tentative and subject to change. RL78/G1A 1. OUTLINE ROM, RAM capacities Flash Data RAM RL78/G1A ROM flash 25 pins 32 pins 48 pins 64 pins 64 4 KB 4 KB R5F10E8E R5F10EBE R5F10EGE R5F10ELE Note KB 48 4 KB 3 KB R5F10E8D R5F10EBD R5F10EGD R5F10ELD KB 32 4 KB 2 KB R5F10E8C R5F10EBC R5F10EGC R5F10ELC KB 16 4 KB 2 KB R5F10E8A R5F10EBA R5F10EGA KB Note This is about 3 KB when the self-programming function and data flash function are used. R01DS0151EJ0001 Rev.0.01 Page 2 of 76 2011.12.26