Datasheet R01DS0246EJ0100 RL78/G1F Rev. 1.00 RENESAS MCU Apr 06, 2015 1. OUTLINE 1.1 Features Ultra-low power consumption technology Event link controller (ELC) Event signals of 22 types can be linked to the specified VDD = single power supply voltage of 1.6 to 5.5 V which peripheral function. can operate a 1.8 V device at a low voltage Serial interfaces HALT mode CSI: 3 to 6 channels STOP mode UART/UART (LIN-bus supported): 3 channels SNOOZE mode 2 2 I C/simplified I C: 3 to 6 channels RL78 CPU core IrDA: 1 channel CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed Timer from high speed (0.03125 s: 32 MHz operation with 16-bit timer: 9 channels high-speed on-chip oscillator) to ultra-low speed (30.5 (Timer Array Unit (TAU): 4 channels, Timer RJ: 1 s: 32.768 kHz operation with subsystem clock) channel, Timer RD: 2 channels (with PWMOPA), Multiply/divide/multiply & accumulate instructions are Timer RG: 1 channel, Timer RX: 1 channel) supported. 12-bit interval timer: 1 channel Address space: 1 MB Real-time clock: 1 channel (calendar for 99 years, alarm General-purpose registers: (8-bit register 8) 4 banks function, and clock correction function) On-chip RAM: 5.5 KB Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) Code flash memory Code flash memory: 32/64 KB A/D converter Block size: 1 KB 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V) Prohibition of block erase and rewriting (security Analog input: 8 to 17 channels function) Internal reference voltage (1.45 V) and temperature On-chip debug function sensor Self-programming (with boot swap function/flash shield D/A converter window function) 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V) Analog output: 1 or 2 channels Data flash memory Data flash memory: 4 KB Output voltage: 0 V to VDD Back ground operation (BGO): Instructions can be Real-time output function executed from the program memory while rewriting the Comparator data flash memory. 2 channels (pin selector is provided for 1 channel) Number of rewrites: 1,000,000 times (TYP.) Incorporates a function for the output of a timer window <R> Voltage of rewrites: VDD = 1.8 to 5.5 V in combination with the timer array unit. The external reference voltage or internal reference High-speed on-chip oscillator Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz, voltage can be selected as the reference voltage. 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and Programmable gain amplifier (PGA) 1 MHz 1 channel High accuracy: 1.0% (VDD = 1.8 to 5.5 V, TA = -20 to +85C) I/O port Operating ambient temperature I/O port: 20 to 58 (N-ch open drain I/O withstand TA = 40 to +85C (A: Consumer applications) voltage of 6 V : 2 to 4, N-ch open drain I/O VDD TA = 40 to +105C (G: Industrial applications) withstand voltage/EVDD withstand voltage : 10 to 16) Can be set to N-ch open drain, TTL input buffer, and on- Power management and reset function chip pull-up resistor On-chip power-on-reset (POR) circuit Different potential interface: Can connect to a 1.8/2.5/3 On-chip voltage detector (LVD) (Select interrupt and V device reset from 14 levels) On-chip key interrupt function On-chip clock output/buzzer output controller Data transfer controller (DTC) Transfer modes: Normal transfer mode, repeat transfer Others mode, block transfer mode On-chip BCD (binary-coded decimal) correction circuit Activation sources: Activated by interrupt sources. Chain transfer function Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01DS0246EJ0100 Rev. 1.00 Page 1 of 140 Apr 06, 2015RL78/G1F 1. OUTLINE ROM, RAM capacities RL78/G1F Flash ROM Data flash RAM 24 pins 32 pins 36 pins 48 pins 64 pins Note 64 KB 4 KB 5.5 KB R5F11B7E R5F11BBE R5F11BCE R5F11BGE R5F11BLE Note 32 KB 4 KB 5.5 KB R5F11B7C R5F11BBC R5F11BCC R5F11BGC R5F11BLC Note This is about 4.5 KB when performing self-programming and rewriting the data flash memory (For details, see CHAPTER 3 CPU ARCHITECTURE in the RL78/G1F Users Manual). R01DS0246EJ0100 Rev. 1.00 Page 2 of 140 Apr 06, 2015