Datasheet R01DS0330EJ0110 RX23E-A Group Rev.1.10 Renesas MCUs Oct 09, 2020 32-MHz, 32-bit RX MCUs with up to 256-KB flash memory, 2 low-noise and low-drift 24-bit delta-sigma A/D converters, rail-to-rail programmable gain instrumentation amplifiers, a low-drift voltage reference, and on-chip excitation current sources Features 32-bit RXv2 CPU core Max. operating frequency: 32 MHz PLQP0048KB-B 7 7 mm, 0.5 mm pitch Capable of 64 DMIPS in operation at 32 MHz Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply- subtract instructions supported Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754) Divider (fastest instruction execution takes two CPU clock cycles) PWQN0040KC-A 6 6 mm, 0.5 mm pitch Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions, ultra-compact code On-chip debugging circuit Up to 12 extended-function timers Memory protection unit (MPU) supported 16-bit MTU: input capture, output compare, complementary PWM Low power design and architecture output, phase counting mode (six channels) Operation from a single 1.8-V to 5.5-V supply 8-bit TMR (four channels) Three low power consumption modes 16-bit compare-match timers (two channels) Low power timer (LPT) that operates during the software standby state Analog functions On-chip flash memory for code Two 24-bit delta-sigma A/D converters Read cycle of 31.25 ns in 32-MHz operation A/D converter with up to 23-bit effective resolution (gain = 1, output No waiting time when the CPU is reading at full speed data rate = 7.6 SPS) 128-Kbyte to 256-Kbyte capacities High-precision programmable gain instrumentation amplifier, On-board or off-board user programming 30 nV (gain = 128, output data rate = 7.6 SPS) RMS Programmable at 1.8 V Rail-to-rail programmable gain instrumentation amplifier For instructions and operands (gain = 1 to 128) On-chip data flash memory Two operating modes and programmable data rates, 8 Kbytes (1,000,000 program/erase cycles (typ.)) Normal mode: Output data rate of 7.6 SPS to 15625 SPS, BGO (Background Operation) Low power mode: Output data rate of 1.9 SPS to 3906 SPS Offset drift 10 nV/C (gain = 128) On-chip SRAM, no wait states Gain drift 1 ppm/C (gain = 1 (PGA), gain = 2 to 128) 16- to 32-Kbyte size capacities Up to six differential inputs, 11 single-ended inputs Data transfer functions Fourth-order sinc filter Simultaneous 50 Hz/60 Hz rejection (output data rate = 10, 54 SPS) DMAC: Incorporates four channels Offset error and gain error calibration DTC: Four transfer modes Inter-unit A/D conversion synchronized start ELC Delta-sigma A/D input disconnect detection assist Module operation can be initiated by event signals without using Delta-sigma A/D reference voltage external input interrupts. Voltage reference Linked operation between modules is possible while the CPU is output voltage: 2.5 V 0.1%, sleeping. temperature drift: 4 ppm/C, output current: 10 mA Reset and supply management Excitation current sources: Up to four, Output current: 50 A to 1000 A, current matching: 0.2%, drift Seven types of reset, including the power-on reset (POR) matching: 5 ppm/C Low voltage detection (LVD) with voltage settings Bias voltage generator Clock functions output voltage: (AVCC0 + AVSS0)/2 Main clock oscillator frequency: 1 MHz to 20 MHz Temperature sensor: Accuracy 5C External clock input frequency: Up to 20 MHz Low-side switch: 10 on-resistance PLL circuit input: 4 MHz to 8 MHz Low power-supply-voltage detectors On-chip low- and high-speed oscillators, dedicated on-chip low-speed Delta-sigma A/D input voltage fault detectors oscillator for the IWDT Delta-sigma A/D reference voltage fault detectors and disconnect Clock frequency accuracy measurement circuit (CAC) detectors Excitation current source disconnect detectors Independent watchdog timer 15-kHz on-chip oscillator produces a dedicated clock signal to drive 12-bit A/D converter IWDT operation. Capable of conversion within 1.4 s Six channels Useful functions for IEC60730 compliance Sampling time can be set for each channel Self-diagnostic and disconnect detection assistance functions for the A/ Self-diagnostic function and analog input disconnect detection D converter, clock frequency accuracy measurement circuit, assistance function independent watchdog timer, RAM test assistance functions using the DOC, etc. General I/O ports 5-V tolerant, open drain, input pull-up, switching of driving capacity MPC Input/output functions selectable from multiple pins Operating temperature range 40C to +85C Up to eight communication functions 40C to +105C CAN (one channel) compliant to ISO11898-1: Transfer at up to 1 Mbps Applications SCI with many useful functions (up to four channels), General industrial and consumer equipment asynchronous mode, clock synchronous mode, smart card interface, reduction of errors in communications using the bit rate modulation function 2 I C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (one channel) RSPI (one channel): Transfer at up to 16 Mbps R01DS0330EJ0110 Rev.1.10 Page 1 of 100 Oct 09, 2020RX23E-A Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/4) Classification Module/Function Description CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU (RX v2) Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 (variable-length instruction format) Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit 32-bit 64-bit On-chip divider: 32-bit 32-bit 32 bits Barrel shifter: 32 bits Memory protection unit (MPU) FPU Single precision (32-bit) floating point Data types and exceptions in conformance with the IEEE754 standard Memory ROM Capacity: 128/256 Kbytes 32 MHz: No-wait access Programming/erasing method: Serial programming (asynchronous serial communication), self-programming RAM Capacity: 16/32 Kbytes 32 MHz, no-wait memory access E2 DataFlash Capacity: 8 Kbytes Number of erase/write cycles: 1,000,000 (typ) MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator Oscillation stop detection: Available Clock frequency accuracy measurement circuit (CAC) Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 32 MHz (at max.) MTU2a runs in synchronization with the PCLKA: 32 MHz (at max.) The ADCLK for the S12AD runs in synchronization with the PCLKD: 32 MHz (at max.) Peripheral modules other than MTU2a and S12AD run in synchronization with the PCLKB: 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) Resets RES pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or detection (LVDAb) internal interrupt is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels R01DS0330EJ0110 Rev.1.10 Page 2 of 100 Oct 09, 2020