Datasheet R01DS0342EJ0110 RX23W Group Rev.1.10 Renesas MCUs Mar 30, 2021 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory, Bluetooth 5.0, various communication functions including USB 2.0 full-speed host/function/OTG, CAN, SD host interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D converter, 12-bit D/A converter, RTC, Encryption functions Features PTBG0085KB-A 5.5 5.5 mm, 0.5 mm pitch 32-bit RXv2 CPU core Max. operating frequency: 54 MHz Capable of 88.56 DMIPS in operation at 54 MHz Enhanced DSP: 32-bit multiply-accumulate and 16-bit PTLG0083KA-A 6.1 9.5 mm, 0.5 mm pitch multiply-subtract instructions supported Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754) Divider (fastest instruction execution takes two CPU clock cycles) PVQN0056LA-A 7 7 mm, 0.4 mm pitch Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions, ultra-compact code Up to 12 communication functions On-chip debugging circuit Bluetooth Low Energy (1 channel) Memory protection unit (MPU) supported An RF transceiver and link layer compliant with the Bluetooth 5.0 Low Low power design and architecture Energy specification Operation from a single 1.8-V to 3.6-V supply LE 1M PHY, LE 2M PHY, LE Coded PHY (125 kbps and 500 kbps), RTC capable of operating on the battery backup power supply and LE Advertising extension support Three low power consumption modes On-chip Bluetooth-dedicated AES-CCM (128-bit blocks) encryption Low power timer (LPT) that operates during the software standby state circuit The 83-pin LGA product has been certified as compliant with radio- On-chip flash memory for code related laws (in Japan, North America, and Europe). 384- to 512-Kbyte capacities The 83-pin LGA product includes a small PCB trace antenna. On-board or off-board user programming USB 2.0 host/function/On-The-Go (OTG) (one channel), Programmable at 1.8 V full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and For instructions and operands BC (Battery Charger) supported On-chip data flash memory CAN (one channel) compliant to ISO11898-1: 8 Kbytes (1,000,000 program/erase cycles (typ.)) Transfer at up to 1 Mbps BGO (Background Operation) SCI with many useful functions (up to 4 channels) On-chip SRAM, no wait states Asynchronous mode, clock synchronous mode, smart card interface 64-Kbyte size capacities Reduction of errors in communications using the bit modulation function Data transfer functions IrDA interface (one channel, in cooperation with the SCI5) DMAC: Incorporates four channels 2 I C bus interface: Transfer at up to 400 kbps, capable of SMBus DTC: Four transfer modes operation (one channel) ELC RSPI (one channel): Transfer at up to 16 Mbps Module operation can be initiated by event signals without using Serial sound interface (one channel) interrupts. SD host interface (optional: one channel) SD memory/ SDIO 1-bit or Linked operation between modules is possible while the CPU is sleeping. 4-bit SD bus supported Reset and supply management Up to 19 extended-function timers Eight types of reset, including the power-on reset (POR) 16-bit MTU: input capture, output compare, complementary PWM Low voltage detection (LVD) with voltage settings output, phase counting mode (five channels) Clock functions 16-bit TPU: input capture, output compare, phase counting mode (six Main clock oscillator frequency: 1 to 20 MHz channels) External clock input frequency: Up to 20 MHz 8-bit TMR (four channels) Sub-clock oscillator frequency: 32.768 kHz 16-bit compare-match timers (four channels) Frequency of Bluetooth-dedicated clock oscillator: 32 MHz 12-bit A/D converter PLL circuit input: 4 MHz to 12.5 MHz Capable of conversion within 0.83 s On-chip low- and high-speed oscillators, dedicated on-chip low-speed 14 channels oscillator for the IWDT Sampling time can be set for each channel USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz Self-diagnostic function and analog input disconnection detection 54 MHz can be set for the system clock and 48 MHz for the USB clock assistance function Generation of a dedicated 32.768-kHz clock for the RTC 12-bit D/A converter Clock frequency accuracy measurement circuit (CAC) Two channels Realtime clock Analog comparator Adjustment functions (30 seconds, leap year, and error) Two channels one unit Calendar count mode or binary count mode selectable Time capture function General I/O ports Time capture on event-signal input through external pins 5-V tolerant, open drain, input pull-up, switching of driving capacity Independent watchdog timer Encryption functions (TSIP-Lite) 15-kHz on-chip oscillator produces a dedicated clock signal to drive Unauthorized access to the encryption engine is disabled and IWDT operation. imposture and falsification of information are prevented Safe management of keys Useful functions for IEC60730 compliance Self-diagnostic and disconnection-detection assistance functions for 128- or 256-bit key length of AES for ECB, CBC, GCM, others True random number generator the A/D converter, clock frequency accuracy measurement circuit, independent watchdog timer, RAM test assistance functions using the Temperature sensor DOC, etc. Operating temperature range Capacitive touch sensing unit 40 to +85C Self-capacitance method: A single pin configures a single key, Applications supporting up to 12 keys 85-pin BGA, 56-pin QFN: General industrial and consumer equipment Mutual capacitance method: Matrix configuration with 12 pins, supporting 83-pin LGA: Consumer equipment up to 36 keys R01DS0342EJ0110 Rev.1.10 Page 1 of 109 Mar 30, 2021RX23W Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/5) Classification Module/Function Description CPU CPU Maximum operating frequency: 54 MHz 32-bit RX CPU (RX v2) Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 (variable-length instruction format) Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit 32-bit 64-bit On-chip divider: 32-bit 32-bit 32 bits Barrel shifter: 32 bits Memory protection unit (MPU) FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory ROM Capacity: 384/512 Kbytes Up to 32 MHz: No-wait memory access 32 to 54 MHz: Wait state required. No wait state if the instruction is served by a ROM accelerator hit. Programming/erasing method: Serial programming (asynchronous serial communication/USB communication), self-programming RAM Capacity: 64 Kbytes 54 MHz, no-wait memory access E2 DataFlash Capacity: 8 Kbytes Number of erase/write cycles: 1,000,000 (typ) MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator, Bluetooth-dedicated clock oscillator, Bluetooth-dedicated low-speed on-chip oscillator Oscillation stop detection: Available Clock frequency accuracy measurement circuit (CAC) Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 54 MHz (at max.) MTU2a runs in synchronization with the PCLKA: 54 MHz (at max.) The ADCLK for the S12AD runs in synchronization with the PCLKD: 54 MHz (at max.) Peripheral modules other than MTU2a and S12ADE run in synchronization with the PCLKB: 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) Resets RES pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt (LVDAb) is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 3 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels R01DS0342EJ0110 Rev.1.10 Page 2 of 109 Mar 30, 2021