Datasheet R01DS0257EJ0200 RX24T Group Rev.2.00 Renesas MCUs Apr 14, 2017 80-MHz 32-bit RX MCUs, on-chip FPU, 153.6 DMIPS, power supply 5 V, 12-bit ADC (equipped with 3-channel synchronous S/H circuits, double data registers, operating amplifiers, comparator) 3 units, Simultaneous sampling up to ADC 5 channels, CAN, 80-MHz PWM (three-phase complementary output 2 channels + single-phase complementary output 4 channels or three-phase complementary 3 channels + single-phase complementary 1 channel) Features 32-bit RXv2 CPU core Max. operating frequency: 80 MHz PLQP0100KB-B 14 x 14 mm, 0.5 mm pitch PLQP0080JA-A 14 x 14 mm, 0.65 mm pitch Capable of 153.6 DMIPS in operation at 80 MHz PLQP0080KB-B 12 x 12 mm, 0.5 mm pitch Enhanced DSP: 32-bit multiply-accumulate and 16-bit PLQP0064KB-C 10 x 10 mm, 0.5 mm pitch multiply-subtract instructions supported Built-in FPU: 32-bit single-precision floating point Up to 6 communications channels (compliant to IEEE754) Divider (fastest instruction execution takes two CPU clock CAN (compliant with ISO11898-1), incorporating cycles) 16 message boxes (1 channel) SCI with many useful functions (3 channels) Fast interrupt Asynchronous mode, clock synchronous mode, smart card CISC Harvard architecture with 5-stage pipeline 2 interface mode, simplified SPI, simplified I C, and Variable-length instructions, ultra-compact code extended serial mode. On-chip debugging circuit 2 Memory protection unit (MPU) supported I C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (1 channel) Low power design and architecture RSPI capable of high speed connection Transfer at up to 20 Operation from a single 2.7-V to 5.5-V supply Mbps (1 channel) Three low power consumption modes Up to 25 extended-function timers On-chip code flash memory 16-bit MTU3: 80 MHz operation, input capture, output 512-/384-/256-/128-Kbyte capacities compare, three-phase complementary PWM 2 channels On-board or off-board user programming output, CPU-efficient complementary PWM, phase For instructions and operands counting mode (nine channels) 16-bit GPT: 80 MHz operation, input capture, output On-chip data flash memory compare, PWM wave-form single-phase complementary 8-Kbyte (Number of erase/write cycles: 1,000,000 (typ)) 4 channels output or three-phase 1 channel + single- BGO (Back Ground Operation) phase complementary 1 channel output, comparator interlocking operation (count operation, PWM negate On-chip SRAM, no wait states control) (4 channels) 32-/16-Kbytes of SRAM 8-bit TMRs (8 channels) Data transfer functions 16-bit compare-match timers (4 channels) DTC: Four transfer modes 12-bit A/D converter: 22 channels in 3 units Reset and supply management Incorporating sample-and-hold circuit 12 bits 3 units (unit 0: 5 channels, unit 1: 5 channels, unit 2: 12 channels) Seven types of reset, including the power-on reset (POR) Sampling time can be set for each channel Low voltage detection (LVD) with voltage settings Group scan priority control mode (3 levels) Clock functions Self-diagnostic function and analog input disconnection Main clock oscillator frequency: 1 to 20 MHz detection assistance function (compliant to IEC60730) External clock input frequency: Up to 20 MHz Input signal amplitude by the programmable gain amplifier PLL circuit input: 4 MHz to 12.5 MHz (4 channels) On-chip low-speed oscillators, On-chip high-speed ADC: 3-channel simultaneous sample-and-hold circuit (3 oscillators, dedicated on-chip oscillator for the IWDT shunt method), double data register (1 shunt method), Clock frequency accuracy measurement circuit (CAC) amplifier (4 channels), comparator (4 channels) Independent watchdog timer 8-bit D/A converter: 2 channels This can be used as reference voltage for a comparator 15-kHz on-chip oscillator produces a dedicated clock signal to drive IWDT operation. Register write protection function can protect Useful functions for IEC60730 compliance values in important registers against overwriting. Self-diagnostic and disconnection-detection assistance functions for the A/D converter, clock frequency accuracy Up to 81 pins for general I/O ports measurement circuit, independent watchdog timer, RAM 5-V tolerant, open drain, input pull-up, switching of test assistance functions using the DOC, etc. driving capacity MPC Operating temperature range Multiple locations are selectable for I/O pins of peripheral 40 to +85C functions Applications General industrial and consumer equipment R01DS0257EJ0200 Rev.2.00 Page 1 of 133 Apr 14, 2017RX24T Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 shows the outline of maximum specifications, and the numbers of peripheral modules and of channels of the modules differ depending on chip version and the pin number on the package. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/4) Classification Module/Function Description CPU CPU Maximum operating frequency: 80 MHz 32-bit RX CPU (RX v2) Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Variable-length instruction format Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit 32-bit 64-bit On-chip divider: 32-bit 32-bit 32-bit Barrel shifter: 32 bits ROM cache: 2 Kbytes (disabled by default) FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory ROM Capacity: 128 K/256 K/384 K/512 Kbytes Up to 32 MHz, no-wait memory access 32 to 80 MHz: wait states Off-board programming Programming/erasing method: Serial programming (asynchronous serial communication), self-programming RAM Capacity: 16 K/32 Kbytes 80 MHz, no-wait memory access E2 DataFlash Capacity: 8 Kbytes Number of erase/write cycles: 1,000,000 (typ) MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, low- and high-speed on-chip oscillators, PLL frequency synthesizer, and IWDT- dedicated on-chip oscillator Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 80 MHz (at max.) The MTU3 and GPT modules run in synchronization with the PCLKA: 80 MHz (at max.) The peripheral modules other than MTU3 and GPT run in synchronization with the PCLKB: 40 MHz (at max.) ADCLK operated in S12AD runs in synchronization with the PCLKD: 40 MHz (at max.) The flash memory peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) Resets RES pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt (LVDAb) is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 3 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels Low power Low power consumption Module stop function consumption functions Three low power consumption modes Sleep mode, deep sleep mode, and software standby mode Function for lower operating Operating power control modes power consumption High-speed operating mode and middle-speed operating mode R01DS0257EJ0200 Rev.2.00 Page 2 of 133 Apr 14, 2017