DatasheetDatasheet R01DS0052EJ0140 RX62N Group, RX621 Group Rev.1.40 Renesas MCUs 2014.07.16 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD, RTC, up to 14 communication channels Features TFLGA85 7 7 mm, 0.65 mm pitch TFLGA145 9 9 mm, 0.65 mm pitch 32-bit RX CPU Core LFBGA176 13 13 mm, 0.8 mm pitch Delivers 165 DMIPS at a maximum operating frequency of 100 MHz Single Precision 32-bit IEEE-754 Floating Point Accumulator: 32 32 to 64-bit result, one instruction Mult/Divide Unit, 32 32 Multiply in one CPU clock for LQFP100 14 14 mm, 0. 5mm pitch multiple instructions LQFP144 20 20 mm, 0.5 mm pitch Interrupt response in as few as 5 CPU clock cycles CISC-Harvard Architecture with 5-stage pipeline Variable length instructions, ultra compact code Up to 14 Communication Interfaces Supports the Memory Protection Unit (MPU) Background JTAG debug plus high-speed trace USB 2.0 Full-Speed interfaces with PHY (2 ch) Supports Host/Function/OTG Low Power Design and Architecture 10 endpoints for types: Control, Interrupt, Bulk, Isochronous Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported. 2.7V to 3.6V operation from a single supply (1 ch) 480 A/MHz Run Mode with all peripherals on Dedicated DMA with 2-Kbyte transmit and receive FIFOs. Deep Software Standby Mode with RTC RMII or MII interface to external PHY Four low power modes CAN ISO11898-1, supports 32 mailboxes (1 ch) SCI channels: Asynchronous, clock sync, smartcard, and 9- Main Flash Memory, no Wait-State bit modes (6 ch) 100 MHz operation, 10 nsec read cycle 2 I C interfaces up to 1 M bps, SMBus support (2 ch) No wait states for read at full CPU speed RSPI (2 ch) 256K, 384K, 512K Byte size options For Instructions or Operands External Address Space Programming from USB, SCI, JTAG, user code Eight CS areas (8 16 Mbytes) 128-Mbyte SDRAM area Data Flash Memory 8-/16-/32-bit bus space selectable for each area Up to 32K Bytes with 30K Erase Cycles Background Erase/Program does not stall CPU TFT-LCD up to WQVGA resolution SRAM, no Wait-State Up to 20 Extended Function Timers 64K or 96K Byte size options 16-bit MTU2 For Operands or Instructions Input capture, Output Compare, PWM output, phase count Back-up retention in Deep Software Standby Mode mode (12 ch) 8-bit TMR (4 ch) DMA 16-bit CMT (4 ch) Four fully programmable internal DMA channels Two EXDMA channels for external-to-external transfers 1-MHz ADC units with two combination choices Data Transfer Controller (DTC) 12-bit 8 ch. unit with single sample/hold circuit or (2) 10-bit 4 ch units each with a sample/hold circuit Reset and Supply Management AD-converted value addition mode (12-bit A/D converter) Power-On Reset (POR) monitor/generator Low Voltage Detect (LVD) with precision setting 10-bit DAC, 2 channels System Clocking with Clock Monitoring Up to 128 GPIO External crystal, 8 MHz to 14 MHz to Internal PLL PLL source to system, USB, and Ethernet 5 V tolerant, Open-Drain, Internal Pull-up Internal 125 kHz LOCO for IWDT External crystal, 32 kHz for RTC Operation Temp 40C to +85C Real Time Clock Full calendar function, BCD format Two Independent Watchdog Timers 125-kHz LOCO operation R01DS0052EJ0140 Rev.1.40 Page 1 of 150 2014.07.16RX62N Group, RX621 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1 Outline of Specifications (1 / 4) Classification Module/Function Description CPU CPU Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits Memory-protection unit (MPU) FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory ROM ROM capacity: 512 Kbytes (max.) Two on-board programming modes Boot mode (The user MAT is programmable via the SCI and USB.) User program mode Parallel programmer mode (for off-board programming) RAM RAM capacity: 96 Kbytes (max.) Data flash Data flash capacity: 32 Kbytes MCU operating modes Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode (software switching) Clock Clock generation Two circuits: Main clock oscillator and subclock oscillator circuit Internal oscillator: Low-speed on-chip oscillator Structure of a PLL frequency synthesizer and frequency divider for selectable operating frequency Oscillation stoppage detection Independent frequency-division and multiplication settings for the system clock (ICLK), peripheral module clock (PCLK), and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): 8 to 100 MHz Peripheral modules run in synchronization with the peripheral module clock (PCLK): 8 to 50 MHz Devices connected to the external bus run in synchronization with the external bus 1 clock (BCLK pin): 8 to 50 MHz* Reset Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset Voltage detection circuit When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or internal interrupt is generated. Low power Low power Module stop function consumption consumption Four low power consumption modes facilities Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode R01DS0052EJ0140 Rev.1.40 Page 2 of 150 2014.07.16