DATASHEET RX62T Group, RX62G Group R01DS0096EJ0200 Renesas MCUs Rev.2.00 100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data Jan 10, 2014 register, amplifier, comparator): two units, 10-bit ADC one unit, the three ADC units are capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary channels and four single-phase complementary channels or three three-phase complementary channels and one single-phase complementary channel) Features 32-bit RX CPU core Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz Single precision 32-bit IEEE-754 floating point Accumulator handles 64-bit results (for a single instruction) from 32- 32-bit operations Multiplication and division unit handles 32- 32-bit PLQP0112JA-A 2020mm, 0.65mm pitch operations (multiplication instructions take one CPU PLQP0100KB-A 1414mm, 0.5mm pitch PLQP0080JA-A 1414mm, 0.65mm pitch clock cycle) PLQP0064KB-A 1010mm, 0.5mm pitch Fast interrupt PLQP0064GA-A 14x14 mm, 0.8mm pitch Divider (fastest instruction execution takes two CPU clock cycles) Up to 7 communications interfaces Fast interrupt 1: CAN (compliant with ISO11898-1), incorporating 32 CISC Harvard architecture with 5-stage pipeline mailboxes Variable-length instructions: Ultra-compact code 3: SCIs, with asynchronous mode (incorporating noise Supports the memory protection unit (MPU) cancellation), clock-synchronous mode, and smart-card Background JTAG debugging plus high-speed tracing interface mode Operating voltage 1: I2C bus interface, capable of SMBus operation Single 3.3- or 5-V supply 5-V analog supply is possible 1: RSPI with 3.3-V products 1: LIN Low-power design and architecture Up to 16 16-bit timers Four low-power modes 8: 16-bit MTU3: 100-MHz operation, input capture, output compare, two three-phase complementary PWM On-chip main flash memory, no wait states output channels, complementary PWM imposing no load 100-MHz operation, 10-ns read cycle on the CPU, phase-counting mode No wait states for reading at full CPU speed 4: 16-bit GPT: 100-MHz operation, input capture, output 64-Kbyte/128-Kbyte/256-Kbyte capacities compare, four complementary single-phase PWM output For instructions and operands channels, or one three-phase complementary PWM User code programmable via the SCI or JTAG output channel and one single-phase complementary PWM output channel, complementary PWM imposing no On-chip data flash memory Max. 32 Kbytes, reprogrammable up to 30,000 times load on the CPU, operation linked with comparator (for Erasing and programming impose no load on the CPU. counting and control of PWM-signal negation), detection of abnormal oscillation frequencies (for IEC 60730 On-chip SRAM, no wait states compliance) 8-Kbyte/16-Kbyte SRAM 4: 16-bit CMT For instructions and operands Generation of delays in PWM waveforms (only for DMA the RX62G Group) DTC: The single unit is capable of transfer on multiple The timing with which signals on the 16-bit GPT PWM channels output pin rise and fall can be controlled with an accuracy of up to 312 ps (in operation at 100 MHz). Reset and supply management Power-on reset (POR) Three A/D converter units for 1-MHz operation, Low voltage detection (LVD) with voltage settings for a total of 20 channels Three units are capable of simultaneous sampling on Clock functions seven channels External crystal oscillator or internal PLL for operation at Self diagnosis (for IEC60730 compliance) 8 to 12.5 MHz 8: Two 12-bit ADC units: three sample-and-hold circuits, Internal 125-kHz LOCO for the IWDT double data registers, amplifier, comparator Detection of main oscillator stoppage (for IEC 60730 12: Single 10-bit ADC unit compliance) CRC (cyclic redundancy check) calculation unit Independent watchdog timer Monitoring of data being transferred (for IEC 60730 (for IEC60730compliance) compliance) 125-kHz LOCO clock operation Monitoring of data in memory (for IEC 60730 Software is incapable of stopping the robust WDT. compliance) Up to 61 inputoutput ports and up to 21 input-only ports PORT registers: Monitoring of output ports (for IEC 60730 compliance) Operating temp. range 40C to +85 C 40C to +105 C R01DS0096EJ0200 Rev.2.00 Page 1 of 134 Jan 10, 2014Preliminary document Under development Specifications in this document are tentative and subject to change. RX62T Group, RX62G Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1 Outline of Specifications (1 / 5) Classification Module/Function Description CPU CPU Maximum operating frequency: 100MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits Memory-protection unit (MPU) FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory ROM ROM capacity: 256 Kbytes (max.) Two on-board programming modes Boot mode (The user MAT is programmable via the SCI) User program mode Off-board programming A PROM programmer can be used to program the user mat. RAM RAM capacity: 16 Kbytes (max.) Data flash Data flash capacity: 32 Kbytes (max.) Supports background operations (BGO) MCU operating mode Single-chip mode Clock Clock generation One circuit: Main clock oscillator circuit Internal oscillator: Low-speed on-chip oscillator dedicated to IWDT Structure of a PLL frequency synthesizer and frequency divider for selectable operating frequency Oscillation stoppage detection Independent frequency-division and multiplication settings for the system clock (ICLK) and peripheral module clock (PCLK) The CPU and system sections such as other bus masters, MTU3, and GPT run in synchronization with the system clock (ICLK): 8 to 100 MHz. Peripheral modules run in synchronization with the peripheral module clock (PCLK): 8 to 50 MHz Reset Pin reset, power-on reset (automatic power-on reset when the power is turned on), voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset Voltage detection circuit (LVD) When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or internal interrupt is generated. Low power Low power Module stop function consumption consumption Four low power consumption modes facilities Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode R01DS0096EJ0200 Rev.2.00 Page 2 of 134 Jan 10, 2014