Features Datasheet RX671 Group R01DS0373EJ0100 Renesas MCUs Rev.1.00 Mar 31, 2021 120-MHz 32-bit RX MCU, on-chip double-precision FPU, 698 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit, 12-bit A/D converter, RTC, Encryption function, Serial sound interface, Remote control signal receiver Features PLQP0144KA-B 20 20 mm, 0.50-mm pitch PLQP0100KB-B 14 14 mm, 0.50-mm pitch PLQP0064KB-C 10 10 mm, 0.50-mm pitch 32-bit RXv3 CPU core Maximum operating frequency: 120 MHz Capable of 698 CoreMark in operation at 120 MHz Double-precision 64-bit IEEE-754 floating point PTLG0145JC-A 9 9 mm, 0.65-mm pitch PTLG0145KB-A 7 7 mm, 0.50-mm pitch A collective register bank save function is available. PTLG0100JB-A 7 7 mm, 0.65-mm pitch Supports the memory protection unit (MPU) JTAG and FINE (one-line) debugging interfaces Low-power design and architecture PTBG0064KB-A 4.5 4.5 mm, 0.50-mm pitch Operation from a single 2.7- to 3.6-V supply Battery supply of backup power allows continued operations of the RTC and the backup registers. Four low-power modes PWQN0048KC-A 7 7 mm, 0.50-mm pitch On-chip code flash memory Supports versions with up to 2 Mbytes of ROM No wait cycles at up to 60 MHz or when the ROM cache is hit, one- Various communications interfaces wait state at up to 120 MHz PHY layer (up to 2 channels) for host/function or OTG controller User code is programmable by on-board or off-board programming. (1 channel) with full-speed USB 2.0 transfer Programming/erasing as background operations (BGOs) CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up A dual-bank structure allows exchanging the start-up bank. to 2 channels) On-chip data flash memory SCIk and SCIh with multiple functionalities (up to 13 channels) 8 Kbytes, reprogrammable up to 100,000 times Choose from among asynchronous mode, clock-synchronous mode, Programming/erasing as background operations (BGOs) 2 C, and smart-card interface mode, simplified SPI, simplified I extended serial mode. On-chip SRAM SCIm with 16-byte transmission and reception FIFOs (up to 2 384 Kbytes of SRAM (no wait states) channels) 4 Kbytes of standby RAM (backup on deep software standby) Up to two RSCIs with Manchester encoding and HBS functionality External address space 2 The I C bus interfaces RIIC and RIICHS for transfer at up to 3.4 Buses for full-speed data transfer (maximum operating frequency of Mbps (up to 3 channels), and the RIICHS also supports high-speed 60 MHz) mode. 8 CS areas Single I/O RSPId (3 channels), single I/O RSPIA (1 channel), and 8- or 16-bit bus space is selectable per area quad QSPIX (1 channel). The QSPIX supports fetching from serial Independent SDRAM area (128 Mbytes) flash memory. Data transfer SD host interface (1 channel) with a 1- or 4-bit SD bus for use with DMACAb: 8 channels SD memory or SDIO DTCb: 1 channel Serial sound interface supporting various audio data formats, 2 EXDMACa: 2 channels including I S Reset and supply management Up to 25 extended-function timers Power-on reset (POR) 16-bit TPUa, MTU3a Low voltage detection (LVD) with voltage settings 8-bit TMRb (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 Backup domain low power detection channels) Clock functions 12-bit A/D converter External crystal resonator or internal PLL for operation at 8 to 24 Two 12-bit units (8 channels for unit 0 12 channels for unit 1) MHz Self diagnosis, detection of analog input disconnection A sub-clock oscillator connectable to a 32.768-kHz crystal resonator Temperature sensor for measuring temperature Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 within the chip MHz 120-kHz clock for the IWDTa Capacitive touch sensing unit Self-capacitance method: A single pin configures a single key, Real-time clock supporting up to 17 keys Adjustment functions (30 seconds, leap year, and error) Mutual capacitance method: Matrix configuration with 17 pins, Real-time clock counting and binary counting modes are selectable supporting up to 64 keys Time capture in response to an event-signal input Encryption function Independent watchdog timer Trusted Secure IP (TSIP) Operates with the 120-kHz clock frequency generated by the AES128/192/256, TDES, ARC4, RSA, ECC, dedicated low-speed oscillator True-random number generator (TRNG), SHA1, SHA224, SHA256, Useful functions for IEC60730 compliance MD5, GHASH, Prevention of the illicit copying of keys Oscillation-stoppage detection, frequency measurement, CRCA, Up to 114 pins for general I/O ports IWDTa, self-diagnostic function for the A/D converter, etc. 5-V tolerance, open drain, input pull-up, switchable driving ability Register write protection function can protect values in important registers against overwriting. Operating temp. range D-version: 40C to +85C Remote control signal receiver G-version: 40C to +105C R01DS0373EJ0100 Rev.1.00 Page 1 of 171 Mar 31, 2021RX671 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different packages. Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/10) Classification Module/Function Description CPU CPU Maximum operating frequency: 120 MHz 32-bit RX CPU (RXv3) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers 113 instructions Instructions installed as standard: 111 Basic instructions: 77 Single-precision floating-point operation instructions: 11 DSP instructions: 23 Instructions for register bank save function: 2 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Double-precision Double-precision floating-point register set floating point Double-precision floating-point data registers: 16, each with 64-bit width coprocessor Double-precision floating-point control registers: Four, each with 32-bit width Double-precision floating-point processing instructions: 21 Notifying the interrupt controller of double-precision floating-point exceptions Register bank save Fast collective saving and restoration of the values of CPU registers function 16 save register banks Memory Code flash memory Capacity: 1 Mbyte/1.5 Mbytes/2 Mbytes ROM cache: 8 Kbytes 60 MHz No-wait cycle access 120 MHz 1-wait cycle access Instructions hitting the ROM cache or operand = 120 MHz: No-wait access On-board programming: Four types Off-board programming (parallel programmer mode) Instructions are executable only for the program stored in the TM target area by using the Trusted Memory (TM) function and protection against data reading is realized. A dual-bank structure allows programming during reading or exchanging the start-up areas Data flash memory Capacity: 8 Kbytes Programming/erasing: 100,000 times Unique ID 16-byte unique ID for the device RAM Capacity: 384 Kbytes 120 MHz, no-wait access Standby RAM Capacity: 4 Kbytes Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access R01DS0373EJ0100 Rev.1.00 Page 2 of 171 Mar 31, 2021