Features Datasheet RX72M Group R01DS0332EJ0111 Renesas MCUs Rev.1.11 Feb 26, 2021 240-MHz 32-bit RX MCU, on-chip double-precision FPU, 1396 CoreMark, Arithmetic unit for trigonometric functions, up to 4-MB flash memory (supportive of the dual bank function), 1-MB SRAM, EtherCAT Slave Controller, various communications interfaces including Ethernet MAC compliant with IEEE 1588, SD host interface, quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), Serial sound interface, CMOS camera interface, Graphic-LCD controller, 2D drawing engine Features PLQP0176KB-C 24 24 mm, 0.5-mm pitch PLQP0144KA-B 20 20 mm, 0.5-mm pitch 32-bit RXv3 CPU core PLQP0100KB-B 14 14 mm, 0.5-mm pitch Maximum operating frequency: 240 MHz Capable of 1396 CoreMark in operation at 240 MHz Double-precision 64-bit IEEE-754 floating point A collective register bank save function is available. PLBG0224GA-A 13 13 mm, 0.8-mm pitch PLBG0176GA-A 13 13 mm, 0.8-mm pitch Supports the memory protection unit (MPU) JTAG and FINE (one-line) debugging interfaces Low-power design and architecture Various communications interfaces Operation from a single 2.7- to 3.6-V supply EtherCAT slave controller (two ports) RTC is capable of operation from a dedicated power supply. Ethernet MAC compliant with IEEE 1588 (2 channels) Four low-power modes PHY layer (1 channel) for host/function or OTG controller On-chip code flash memory (1 channel) with full-speed USB 2.0 transfer CAN (compliant with ISO11898-1), incorporating 32 mailboxes (3 Supports versions with up to 4 Mbytes of ROM channels) No wait cycles at up to 120 MHz or when the ROM cache is hit, SCIj and SCIh with multiple functionalities (8 channels) one-wait state at above 120 MHz Choose from among asynchronous mode, clock-synchronous mode, User code is programmable by on-board or off-board programming. 2 Programming/erasing as background operations (BGOs) smart-card interface mode, simplified SPI, simplified I C, and A dual-bank structure allows exchanging the start-up bank. extended serial mode. SCIi with 16-byte transmission and reception FIFOs (5 channels) On-chip data flash memory 2 I C bus interface for transfer at up to 1 Mbps (3 channels) 32 Kbytes, reprogrammable up to 100,000 times Four-wire QSPI (1 channel) in addition to RSPIc (3 channels) Programming/erasing as background operations (BGOs) Parallel data capture unit (PDC) for the CMOS camera interface On-chip SRAM Graphic-LCD controller (GLCDC) 1 Mbyte of SRAM (no wait states however, if ICLK is at a 2D drawing engine (DRW2D) frequency above 120 MHz, access to locations in the 512 Kbytes of SD host interface (1 channel) with a 1- or 4-bit SD bus for use with SRAM from 0080 0000h to 0087 FFFFh requires one cycle of SD memory or SDIO waiting) MMCIF with 1-, 4-, or 8-bit transfer bus width 32 Kbytes of RAM with ECC (single error correction/double error External address space detection) Buses for full-speed data transfer (max. operating frequency of 80 8 Kbytes of standby RAM (backup on deep software standby) MHz) Data transfer 8 CS areas DMACAa: 8 channels 8-, 16-, or 32-bit bus space is selectable per area DTCb: 1 channel Independent SDRAM area (128 Mbytes) EXDMAC: 2 channels Up to 29 extended-function timers DMAC for the Ethernet controller: 3 channels 32-bit GPTW (4 channels) Reset and supply management 16-bit TPUa (6 channels), MTU3a (9 channels) Power-on reset (POR) 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 Low voltage detection (LVD) with voltage settings channels) Clock functions 12-bit A/D converter External crystal resonator or internal PLL for operation at 8 to 24 Two 12-bit units (8 channels for unit 0 21 channels for unit 1) MHz Self diagnosis, detection of analog input disconnection PLL for specific purposes 12-bit D/A converter: 2 channels Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz Temperature sensor for measuring temperature 120-kHz clock for the IWDTa within the chip Real-time clock Arithmetic unit for trigonometric functions Adjustment functions (30 seconds, leap year, and error) Delta-Sigma Modulator Interface Real-time clock counting and binary counting modes are selectable Six external delta-sigma modulators are connectable Time capture function (for capturing times in response to event-signal input) Encryption functions (optional) AES (key lengths: 128, 192, and 256 bits) Independent watchdog timer Trusted Secure IP (TSIP) 120-kHz clock operation Up to 182 pins for general I/O ports Useful functions for IEC60730 compliance 5-V tolerance, open drain, input pull-up, switchable driving ability Oscillation-stoppage detection, frequency measurement, CRCA, IWDTa, self-diagnostic function for the A/D converter, etc. Operating temp. range Register write protection function can protect values in important D-version: 40 C to +85C registers against overwriting. G-version: 40 C to +105C R01DS0332EJ0111 Rev.1.11 Page 1 of 180 Feb 26, 2021RX72M Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different packages. Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details, refer to Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/11) Classification Module/Function Description CPU CPU Maximum operating frequency: 240 MHz 32-bit RX CPU (RXv3) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers 113 instructions Instructions installed as standard: 111 Basic instructions: 77 Single-precision floating-point operation instructions: 11 DSP instructions: 23 Instructions for register bank save function: 2 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits FPU Single-precision floating-point numbers (32 bits) and double-precision floating-point numbers (64 bits) Data types and floating-point exceptions in conformance with the IEEE754 standard Double-precision Double-precision floating-point register set floating point Double-precision floating-point data registers: 16, each with 64-bit width coprocessor Double-precision floating-point control registers: Four, each with 32-bit width Double-precision floating-point processing instructions: 21 Notifying the interrupt controller of double-precision floating-point exceptions Register bank save Fast collective saving and restoration of the values of CPU registers function 16 save register banks R01DS0332EJ0111 Rev.1.11 Page 2 of 180 Feb 26, 2021