Features Datasheet RX72N Group R01DS0343EJ0111 Renesas MCUs Rev.1.11 Feb 26, 2021 240-MHz 32-bit RX MCU, on-chip double-precision FPU, 1396 CoreMark, Arithmetic unit for trigonometric functions, up to 4-MB flash memory (supportive of the dual bank function), 1-MB SRAM, various communications interfaces including Ethernet MAC compliant with IEEE 1588, SD host interface, quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), Serial sound interface, CMOS camera interface, Graphic-LCD controller, 2D drawing engine Features PLQP0176KB-C 24 24 mm, 0.5-mm pitch PLQP0144KA-B 20 20 mm, 0.5-mm pitch PLQP0100KB-B 14 14 mm, 0.5-mm pitch 32-bit RXv3 CPU core Maximum operating frequency: 240 MHz Capable of 1396 CoreMark in operation at 240 MHz Double-precision 64-bit IEEE-754 floating point PTLG0145KA-A 7 7 mm, 0.5-mm pitch A collective register bank save function is available. Supports the memory protection unit (MPU) JTAG and FINE (one-line) debugging interfaces Low-power design and architecture Operation from a single 2.7- to 3.6-V supply PLBG0224GA-A 13 13 mm, 0.8-mm pitch PLBG0176GA-A 13 13 mm, 0.8-mm pitch RTC is capable of operation from a dedicated power supply. Four low-power modes On-chip code flash memory Various communications interfaces Supports versions with up to 4 Mbytes of ROM Ethernet MAC compliant with IEEE 1588 (2 channels) No wait cycles at up to 120 MHz or when the ROM cache is hit, PHY layer (1 channel) for host/function or OTG controller one-wait state at above 120 MHz (1 channel) with full-speed USB 2.0 transfer User code is programmable by on-board or off-board programming. CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up Programming/erasing as background operations (BGOs) to 3 channels) A dual-bank structure allows exchanging the start-up bank. SCIj and SCIh with multiple functionalities (up to 8 channels) Choose from among asynchronous mode, clock-synchronous mode, On-chip data flash memory 2 smart-card interface mode, simplified SPI, simplified I C, and 32 Kbytes, reprogrammable up to 100,000 times extended serial mode. Programming/erasing as background operations (BGOs) SCIi with 16-byte transmission and reception FIFOs (up to 5 On-chip SRAM channels) 1 Mbyte of SRAM (no wait states however, if ICLK is at a 2 I C bus interface for transfer at up to 1 Mbps (3 channels) frequency above 120 MHz, access to locations in the 512 Kbytes of Four-wire QSPI (1 channel) in addition to RSPIc (3 channels) SRAM from 0080 0000h to 0087 FFFFh requires one cycle of Parallel data capture unit (PDC) for the CMOS camera interface waiting) (except for 100-pin products) 32 Kbytes of RAM with ECC (single error correction/double error Graphic-LCD controller (GLCDC) detection) 2D drawing engine (DRW2D) 8 Kbytes of standby RAM (backup on deep software standby) SD host interface (1 channel) with a 1- or 4-bit SD bus for use with SD memory or SDIO Data transfer MMCIF with 1-, 4-, or 8-bit transfer bus width DMACAa: 8 channels DTCb: 1 channel External address space EXDMAC: 2 channels Buses for full-speed data transfer (max. operating frequency of 80 DMAC for the Ethernet controller: 3 channels MHz) Reset and supply management 8 CS areas 8-, 16-, or 32-bit bus space is selectable per area Power-on reset (POR) Independent SDRAM area (128 Mbytes) Low voltage detection (LVD) with voltage settings Up to 29 extended-function timers Clock functions 32-bit GPTW (4 channels) External crystal resonator or internal PLL for operation at 8 to 24 MHz 16-bit TPUa (6 channels), MTU3a (9 channels) PLL for specific purposes 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 channels) MHz 12-bit A/D converter 120-kHz clock for the IWDTa Two 12-bit units (8 channels for unit 0 21 channels for unit 1) Real-time clock Self diagnosis, detection of analog input disconnection Adjustment functions (30 seconds, leap year, and error) 12-bit D/A converter: 2 channels Real-time clock counting and binary counting modes are selectable Time capture function Temperature sensor for measuring temperature (for capturing times in response to event-signal input) within the chip Independent watchdog timer Arithmetic unit for trigonometric functions 120-kHz clock operation Encryption functions (optional) Useful functions for IEC60730 compliance AES (key lengths: 128, 192, and 256 bits) Oscillation-stoppage detection, frequency measurement, CRCA, Trusted Secure IP (TSIP) IWDTa, self-diagnostic function for the A/D converter, etc. Up to 182 pins for general I/O ports Register write protection function can protect values in important 5-V tolerance, open drain, input pull-up, switchable driving ability registers against overwriting. Operating temp. range D-version: 40 C to +85C G-version: 40 C to +105C R01DS0343EJ0111 Rev.1.11 Page 1 of 179 Feb 26, 2021RX72N Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different packages. Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details, refer to Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/11) Classification Module/Function Description CPU CPU Maximum operating frequency: 240 MHz 32-bit RX CPU (RXv3) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers 113 instructions Instructions installed as standard: 111 Basic instructions: 77 Single-precision floating-point operation instructions: 11 DSP instructions: 23 Instructions for register bank save function: 2 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits FPU Single-precision floating-point numbers (32 bits) and double-precision floating-point numbers (64 bits) Data types and floating-point exceptions in conformance with the IEEE754 standard Double-precision Double-precision floating-point register set floating point Double-precision floating-point data registers: 16, each with 64-bit width coprocessor Double-precision floating-point control registers: Four, each with 32-bit width Double-precision floating-point processing instructions: 21 Notifying the interrupt controller of double-precision floating-point exceptions Register bank save Fast collective saving and restoration of the values of CPU registers function 16 save register banks R01DS0343EJ0111 Rev.1.11 Page 2 of 179 Feb 26, 2021