Datasheet R01DS0369EJ0100 RE01 Group (256-KB Flash Memory) Rev.1.00 Renesas Microcontrollers Apr 3, 2020 64 MHz, 32-bit Arm Cortex -M0+, 256-KB flash memory, 128-KB SRAM, energy harvesting control circuit, MIP LCD controller, 2D graphic engine, 14-bit ultra-low power consumption A/D converter, VREF circuit, RTC, sub-clock correction circuit (theoretical regulation), security function (optional), SPI, quad SPI Features Arm Cortex-M0+ core incorporated Maximum operating frequency: 64 MHz PLQP0100KB-B Arm Memory Protection Unit (Arm MPU) with 8 regions 14 14mm, 0.5-mm pitch CoreSight Debug Port: SW-DP PLQP0064KB-A 10 10mm, 0.5-mm pitch Power-aving functions Back-bias control function based on silicon-on-thin-buried-oxide (SOTB ) process technology Operation at ultra-low power-supply voltages (from 1.62 V to 3.6 Various analog circuits V) Single 14-bit successive approximation A/D converter Three power control modes based on the operating frequency High precision: 8 channels, standard precision: 4 channels Four low power consumption modes Single temperature sensor for measuring the internal temperature of Three power supply modes the chip VREF circuit for the 14-bit A/D converter reference voltage On-chip Code flash memory 256-Kbyte code flash memory Various timer circuits No cycles of waiting for access in operation at or below 32 MHz Six general PWM timers (GPT) one cycle of waiting at frequencies above 32 MHz Two 32-bit counters Function for area protection prevents erroneous overwriting or Four 16-bit counters tampering Four asynchronous general-purpose timers (AGT) that can be used in standby mode On-chip SRAM Two 32-bit counters 128-Kbyte SRAM with no access wait cycles Two 16-bit counters Two 8-bit timers (TMR) Data transfer Single realtime clock (RTC) Four DMA controllers Single watchdog timer (WDT) Single data transfer controller (DTC) Single low-speed timer (LST) that operates at 1 kHz A circuit for converting hexadecimal numbers to decimal numbers Reset and supply management for use as a stopwatch Power-on reset (POR) Human machine interfaces Low voltage detection (LVD) can be set. Single memory-in-pixel (MIP) LCD controller (MLCD) Parallel Multiple clock sources interface is supported. Single 2D graphics data conversion circuit (GDT) External crystal oscillator (main clock): 8 to 32 MHz External crystal oscillator (sub-clock): 32.768 kHz Security functions (optional) High-speed on-chip oscillator (HOCO): 24, 32, 48, or 64 MHz Middle-speed on-chip oscillator (MOCO): 2 MHz Single Trusted Secure IP Lite (TSIP) Low-speed on-chip oscillator (LOCO): 32 kHz AES (128- or 256-bit key length, supporting ECB, CBC, CMAC, Independent watchdog timer on-chip oscillator: 16 kHz GCM, and others) Key wrapping protects against the leakage of the encryption keys Energy harvesting control of users. An access management circuit disables illicit access to the A power generation element is directly connectable. encryption engine. High-speed startup is possible without having to wait for the Using the other security functions together with area protection charging of a secondary battery. enables secure booting and secure over-the-air (OTA) software Function to prevent a secondary battery from overcharging updates. Independent watchdog timer Operating voltage and temperature range 14-bit counter, 16-kHz (1/2 LOCO clock frequency) operation VCC = IOVCC = IOVCCn= AVCC0 = 1.62 V to 3.6 V IOVCCn and AVCC0 can each be independently set to a voltage Sub-clock correction circuit (CCC) within the range between 1.62 V and 3.6 V. The CCC corrects the accuracy of oscillation every 16 seconds Ta: 40 to +85C (theoretical regulation). Events can be generated per second in deep software standby mode. Communication functions Two serial peripheral interfaces Single 128-bit buffer for which up to eight commands can be specified Single 32-bit buffer for which one command can be specified Single quad serial peripheral interface connectable to an external flash memory 2 Two I C bus interfaces Five serial communications interfaces (SCIg) 2 Asynchronous, clock-synchronous, simple I C, simple SPI, and smart card interfaces, and IrDA interface version 1.0 (the latter is only applicable to SCI0) Two serial communication interfaces (SCIi) each having a 16-byte FIFO R01DS0369EJ0100 Rev.1.00 Page 1 of 101 Apr 3, 2020RE01 Group (256-KB Flash Memory) 1. Overview 1. Overview 1.1 Function Outline Table 1.1 to Table 1.11 show the outline of maximun specifications. Tthe number of peripheral channels differs depending on the number of pins of the package. For details, see Table 1.13. Table 1.1 Arm core Feature Functional description Maximum operating frequency: up to 64 MHz Arm Cortex -M0+ core Arm Cortex-M0+ core: Revision: r0p1-00rel0 Armv6-M architecture profile Single-cycle integer multiplier Arm Memory Protection Unit (MPU): Armv6 Protected Memory System Architecture Eight protect regions SysTick timer: Driven by SYSTICCLK (LOCO or ICLK) Table 1.2 Memory Feature Functional description Code flash memory Maximum 256 KB of code flash memory. No cycles of waiting for access in operation at or below 32 MHz one cycle of waiting at frequencies above 32 MHz Prefetch function On-board programming (three types): Programming in serial programming mode (SCI boot mode) Programming in on-chip debug mode Programming by a routine for code flash memory rewriting within a user program SRAM Maximum 128 KB of SRAM SRAM0: 0x2000 0000 to 0x2000 7FFF SRAM1: 0x2000 8000 to 0x2001 FFFF Both areas are available during low leakage current mode. 64 MHz, No cycles of waiting for access Table 1.3 System (1 of 2) Feature Functional description Startup modes Three startup modes: Normal startup mode Energy harvesting startup mode SCI boot mode Resets The MCU provides 13 resets. The resets are classified into two types: System resets that initialize the MCU and power shutdown reset that does not initialize the MCU. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin and VBAT EHC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVDBAT). LVD0 and LVD1 measure the voltage level input to the VCC pin, and LVDBAT measures the voltage level input to the VBAT EHC pin. LVD registers allow your application to configure detection of VCC and VBAT EHC changes at various voltage thresholds. Clocks The MCU has the following clock generation circuits. Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) High-speed on-chip oscillator (HOCO) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) IWDT-dedicated on-chip oscillator (IWDTLOCO) Clock output support CLKOUT pin (capable of outputting all types of clock signals) CLKOUT32K pin (capable of outputting SOSC clock signals) R01DS0369EJ0100 Rev.1.00 Page 2 of 101 Apr 3, 2020