Datasheet R01DS0386EJ0110 RA2E1 Group Rev.1.10 Renesas Microcontrollers Dec 28, 2020 Ultra low power 48 MHz Arm Cortex -M23 core, up to 128-KB code flash memory, 16-KB SRAM, Capacitive Sensing Unit 2 (CTSU), 12-bit A/D Converter, Security and Safety features. Features IWDT-dedicated on-chip oscillator (15 kHz) Arm Cortex-M23 Core Clock out support Armv8-M architecture Maximum operating frequency: 48 MHz Up to 56 pins for general I/O ports Arm Memory Protection Unit (Arm MPU) with 8 regions 5-V tolerance, open drain, input pull-up, switchable driving ability Debug and Trace: DWT, FPB, CoreSight MTB-M23 CoreSight Debug Port: SW-DP Operating Voltage VCC: 1.6 to 5.5 V Memory Up to 128-KB code flash memory Operating Temperature and Packages 4-KB data flash memory (100,000 program/erase (P/E) cycles) Ta = -40 to +85 16-KB SRAM 64-pin LQFP (14 mm 14 mm, 0.8 mm pitch) Memory protection units 128-bit unique ID 64-pin LQFP (10 mm 10 mm, 0.5 mm pitch) 64-pin BGA (4 mm 4 mm, 0.4 mm pitch) Connectivity 48-pin LQFP (7 mm 7 mm, 0.5 mm pitch) 48-pin HWQFN (7 mm 7 mm, 0.5 mm pitch) Serial Communications Interface (SCI) 4 36-pin LGA (4 mm 4 mm, 0.5 mm pitch) Asynchronous interfaces 32-pin LQFP (7 mm 7 mm, 0.8 mm pitch) 8-bit clock synchronous interface 32-pin HWQFN (5 mm 5 mm, 0.5 mm pitch) Simple IIC 25-pin WLCSP (2.14 mm 2.27 mm, 0.4 mm pitch) Simple SPI Ta = -40 to +105 Smart card interface 64-pin LQFP (14 mm 14 mm, 0.8 mm pitch) Serial Peripheral Interface (SPI) 1 64-pin LQFP (10 mm 10 mm, 0.5 mm pitch) 2 I C bus interface (IIC) 1 64-pin BGA (4 mm 4 mm, 0.4 mm pitch) 48-pin LQFP (7 mm 7 mm, 0.5 mm pitch) Analog 48-pin HWQFN (7 mm 7 mm, 0.5 mm pitch) 12-bit A/D Converter (ADC12) 36-pin LGA (4 mm 4 mm, 0.5 mm pitch) Low-Power Analog Comparator (ACMPLP) 2 32-pin LQFP (7 mm 7 mm, 0.8 mm pitch) Temperature Sensor (TSN) 32-pin HWQFN (5 mm 5 mm, 0.5 mm pitch) 25-pin WLCSP (2.14 mm 2.27 mm, 0.4 mm pitch) Timers General PWM Timer 32-bit (GPT32) 1 General PWM Timer 16-bit (GPT16) 6 Low Power Asynchronous General Purpose Timer (AGT) 2 Watchdog Timer (WDT) Safety SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access detection Security and Encryption AES128/256 True Random Number Generator (TRNG) System and Power Management Low power modes Switching regulator Realtime Clock (RTC) Event Link Controller (ELC) Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low Voltage Detection (LVD) with voltage settings Human Machine Interface (HMI) Capacitive Sensing Unit 2 (CTSU) Multiple Clock Sources Main clock oscillator (MOSC) 1 to 20 MHz Sub-clock oscillator (SOSC) (32.768 kHz) High-speed on-chip oscillator (HOCO) (24/32/48/64 MHz) Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) Clock trim function for HOCO/MOCO/LOCO R01DS0386EJ0110 Rev.1.10 Page 1 of 112 Dec 28, 2020RA2E1 Datasheet 1. Overview 1. Overview The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability. The MCU in this series incorporates an energy-efficient Arm Cortex -M23 32-bit core, that is particularly well suited for cost-sensitive and low-power applications, with the following features: Up to 128-KB code flash memory 16-KB SRAM 12-bit A/D Converter (ADC12) Security features 1.1 Function Outline Table 1.1 Arm core Feature Functional description Arm Cortex-M23 core Maximum operating frequency: up to 48 MHz Arm Cortex-M23 core: Revision: r1p0-00rel0 Armv8-M architecture profile Single-cycle integer multiplier 19-cycle integer divider Arm Memory Protection Unit (Arm MPU): Armv8 Protected Memory System Architecture 8 protect regions SysTick timer: Driven by SYSTICCLK (LOCO) or ICLK Table 1.2 Memory Feature Functional description Code flash memory Maximum 128-KB of code flash memory. Data flash memory 4-KB of data flash memory. Option-setting memory The option-setting memory determines the state of the MCU after a reset. SRAM On-chip high-speed SRAM with parity bit. Table 1.3 System (1 of 2) Feature Functional description Operating modes Two operating modes: Single-chip mode SCI boot mode Resets The MCU provides 12 resets (RES pin reset, power-on reset, independent watchdog timer reset, watchdog timer reset, voltage monitor 0/1/2 resets, SRAM parity error reset, bus master/slave MPU error resets, CPU stack pointer error reset, software reset). Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level input to the VCC pin. LVD registers allow your application to configure detection of VCC changes at various voltage thresholds. Clocks Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) High-speed on-chip oscillator (HOCO) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) IWDT-dedicated on-chip oscillator Clock out support R01DS0386EJ0110 Rev.1.10 Page 2 of 112 Dec 28, 2020