Datasheet Cover Renesas RA6M3 Group 32 Datasheet 32-Bit MCU Renesas Advanced (RA) Family Renesas RA6 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (RA6M3 Group Datasheet Leading performance 120-MHz Arm Cortex -M4 core, up to 2-MB code flash memory, 640-KB SRAM, Graphics LCD Controller, 2D Drawing Engine, Capacitive Touch Sensing Unit, Ethernet MAC Controller with IEEE 1588 PTP, USB 2.0 High-Speed, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog. Features Arm Cortex-M4 Core with Floating Point Unit (FPU) System and Power Management Armv7E-M architecture with DSP instruction set Low power modes Maximum operating frequency: 120 MHz Realtime Clock (RTC) with calendar and VBATT support Support for 4-GB address space Event Link Controller (ELC) On-chip debugging system: JTAG, SWD, and ETM DMA Controller (DMAC) 8 Boundary scan and Arm Memory Protection Unit (Arm MPU) Data Transfer Controller (DTC) Key Interrupt Function (KINT) Memory Power-on reset Up to 2-MB code flash memory (40 MHz zero wait states) Low Voltage Detection (LVD) with voltage settings 64-KB data flash memory (125,000 erase/write cycles) Security and Encryption Up to 640-KB SRAM Flash Cache (FCACHE) AES128/192/256 Memory Protection Units (MPU) 3DES/ARC4 Memory Mirror Function (MMF) SHA1/SHA224/SHA256/MD5 128-bit unique ID GHASH RSA/DSA/ECC Connectivity True Random Number Generator (TRNG) Ethernet MAC Controller (ETHERC) Human Machine Interface (HMI) Ethernet DMA Controller (EDMAC) Ethernet PTP Controller (EPTPC) Graphics LCD Controller (GLCDC) USB 2.0 High-Speed (USBHS) module JPEG codec - On-chip transceiver with voltage regulator 2D Drawing Engine (DRW) - Compliant with USB Battery Charging Specification 1.2 Capacitive Touch Sensing Unit (CTSU) USB 2.0 Full-Speed (USBFS) module Parallel Data Capture Unit (PDC) - On-chip transceiver with voltage regulator Multiple Clock Sources Serial Communications Interface (SCI) with FIFO 10 Main clock oscillator (MOSC) (8 to 24 MHz) Serial Peripheral Interface (SPI) 2 Sub-clock oscillator (SOSC) (32.768 kHz) 2 I C bus interface (IIC) 3 High-speed on-chip oscillator (HOCO) (16/18/20 MHz) Controller Area Network (CAN) 2 Middle-speed on-chip oscillator (MOCO) (8 MHz) Serial Sound Interface Enhanced (SSIE) 2 Low-speed on-chip oscillator (LOCO) (32.768 kHz) SD/MMC Host Interface (SDHI) 2 IWDT-dedicated on-chip oscillator (15 kHz) Quad Serial Peripheral Interface (QSPI) Clock trim function for HOCO/MOCO/LOCO IrDA interface Clock out support Sampling Rate Converter (SRC) General-Purpose I/O Ports External address space - 8-bit or 16-bit bus space is selectable per area Up to 133 input/output pins - SDRAM support - Up to 9 CMOS input - Up to 124 CMOS input/output Analog - Up to 21 input/output 5 V tolerant 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits - Up to 18 high current (20 mA) each 2 Operating Voltage 12-bit D/A Converter (DAC12) 2 High-Speed Analog Comparator (ACMPHS) 6 VCC: 2.7 to 3.6 V Programmable Gain Amplifier (PGA) 6 Operating Temperature and Packages Temperature Sensor (TSN) Ta = -40C to +85C Timers - 176-pin BGA (13 mm 13 mm, 0.8 mm pitch) General PWM Timer 32-bit Enhanced High Resolution - 145-pin LGA (7 mm 7 mm, 0.5 mm pitch) (GPT32EH) 4 Ta = -40C to +105C General PWM Timer 32-bit Enhanced (GPT32E) 4 - 176-pin LQFP (24 mm 24 mm, 0.5 mm pitch) General PWM Timer 32-bit (GPT32) 6 - 144-pin LQFP (20 mm 20 mm, 0.5 mm pitch) Asynchronous General-Purpose Timer (AGT) 2 - 100-pin LQFP (14 mm 14 mm, 0.5 mm pitch) Watchdog Timer (WDT) Safety Error Correction Code (ECC) in SRAM SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access R01DS0358EJ0110 Rev.1.10 Page 2 of 116 Dec 25, 2020