ICSSSTVF16859B DDR 13-Bit to 26-Bit Registered Buffer Recommended Applications: Pin Configuration DDR Memory Modules: Q13A 1 64 VDDQ - DDRI (PC1600, PC2100) 2 63 Q12A GND - DDR333 (PC2700) Q11A 3 62 D13 Q10A 4 61 D12 - DDRI-400 (PC3200) Q9A 5 60 VDD Provides complete DDR DIMM logic solution with VDDQ 6 59 VDDQ GND 7 58 GND ICS93V857 or ICS95V857 Q8A 8 57 D11 SSTL 2 compatible data registers Q7A 9 56 D10 Q6A 10 55 D9 Q5A 11 54 GND Product Features: Q4A 12 53 D8 Q3A 13 52 D7 Differential clock signals Q2A 14 51 RESET GND 15 50 GND Meets SSTL 2 signal data 16 Q1A 49 CLK Supports SSTL 2 class I specifications on outputs Q13B 17 48 CLK VDDQ 18 47 VDDQ Low-voltage operation 19 46 Q12B VDD - V = 2.3V to 2.7V DD Q11B 20 45 VREF Q10B 21 44 D6 Available in 64 pin TSSOP and 56 pin MLF packages Q9B 22 43 GND Q8B 23 42 D5 1 Truth Table Q7B 24 41 D4 Q6B 25 40 D3 GND 26 39 GND Isnputs Q Output VDDQ 27 38 VDDQ RKESET C L CDLK Q Q5B 28 37 VDD Q4B 29 36 D2 X or X or X or 30 Q3B 35 D1 L L Floating Floating Floating Q2B 31 34 GND Q1B 32 33 VDDQ H HH H LL 64-Pin TSSOP (2) HHLHor LXor Q 0 6.10 mm. Body, 0.50 mm. pitch Notes: 1. H =Hig Signal Level L =Lo Signal Level 43 56 = TransitionLo-toHig = TransitionHig-toLo 1 Q7A 42 D10 X = Don t Care Q6A D9 Q5A D8 2. Output level before the indicated steady state Q4A input conditions were established. D7 Q3A RESET Block Diagram Q2A GND Q1A CLK ICSSSTVF16859B Q13B CLK CLK VDDQ VDDQ CLK Q12B VDD Q11B VREF RESET R Q1A Q10B D6 CLK Q9B D5 D1 Q1B D1 14 29 Q8B D4 VREF 15 28 To 12 Other Channels 56-pin FVQFN (MLF2) 1019B03/15/05 Q7B Q8A Q6B VDDQ VDDQ Q9A Q5B Q10A Q4B Q11A Q3B Q12A Q2B Q13A ICSSSTVF16859B Q1B VDDQ VDDQ GND D1 D13 D2 D12 VDD VDD VDDQ VDDQ D3 D11ICSSSTVF16859B General Description The 13-bit-to-26-bit ICSSSTVF16859B is a universal bus driver designed for 2.3V to 2.7V V operation and SSTL 2 DD I/O levels, except for the LVCMOS RESET input. Data flow from D to Q is controlled by the differential clock (CLK/CLK ) and a control signal (RESET ). The positive edge of CLK is used to trigger the data flow and CLK is used to maintain sufficient noise margins where as RESET , an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVF16859B supports low- power standby operation. A logic level Low at RESET assures that all internal registers and outputs (Q) are reset to the logic Low state, and all input receivers, data (D) and clock (CLK/CLK ) are switched off. Please note that RESET must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET must be held at a logic Low level during power up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK . Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic Low level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level Low and the clock is stable during the Low-to-High transition of RESET until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic Low level. Pin Configuration (64-Pin TSSOP) PEIN NUMBER PEIN NAMTNYP DESCRIPTIO 1)-5, 8-14, 16, 17, 19-25, 28-32QT(13:1OtUTPU Data outpu 7, 15, 26, 34, 39, 43, 50, 54, GRND PdW Groun 58, 63 6Q, 18, 27, 33, 38, 47, 59, 64VRDDPlW Output supply voltage, 2.5V nomina 35, 36, 40-42, 44, 52, 53, 55- DT(13:1)ItNPU Data inpu 57, 61, 62 4K8 CTLItNPU Positive master clock inpu 4 9 CTLKItNPU Negative master clock inpu 3D7, 46, 60 VRDPlW Core supply voltage, 2.5V nomina 5 1 RTESETI)NPU Reset (active low 4F5 VTREIlNPU Input reference voltage, 2.5V nomina Pin Configuration (56-Pin MLF2) PEIN NUMBER PEIN NAMTNYP DESCRIPTIO 1)-8, 10-16, 18-22, 50-54, 56QT(13:1OtUTPU Data outpu 3D7, 48 GRN PdW Groun 9Q, 17, 23, 27, 34, 44, 49, 55VRDDPlW Output supply voltage, 2.5V nomina 2)4, 25, 28-31, 39-43, 46, 47DT(13:1ItNPU Data inpu 3K5 CTLItNPU Positive master clock inpu 3 6 CTLKItNPU Negative master clock inpu 2D6, 33, 45 VRDPlW Core supply voltage, 2.5V nomina 3 8 RTESETI)NPU Reset (active low 3F2 VTREIlNPU Input reference voltage, 2.5V nomina -DCRenter PAP)W Ground (MLF2 package only 1019B03/15/05 2