74FCT163374APAG8 Renesas

IDT74FCT163374A/C 3.3V CMOS 16-BIT REGISTER (3-STATE) INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74FCT163374A/C REGISTER (3-STATE) FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT163374 16-bit edge-triggered D-type register is built using Typical tSK(o) (Output Skew) < 250ps advanced dual metal CMOS technology. These high-speed, low-power ESD > 2000V per MIL-STD-883, Method 3015 > 200V using registers are ideal for use as buffer registers for data synchronization and machine model (C = 200pF, R = 0) storage. The Output Enable (xOE) and clock (xCLK) controls are organized VCC = 3.3V 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended to operate each device as two 8-bit registers or one 16-bit register with Range common clock. Flow-through organization of signal pins facilitates ease of CMOS power levels (0.4 W typ. static) layout. All inputs are designed with hysteresis for improved noise margin. Rail-to-rail output swing for increased noise margin The inputs of FCT163374 can be driven from either 3.3V or 5V devices. Low Ground Bounce (0.3V typ.) This feature allows the use of these devices as translators in a mixed 3.3V/ Inputs (except I/O) can be driven by 3.3V or 5V components 5V supply system. Available in SSOP and TSSOP packages FUNCTIONAL BLOCK DIAGRAM 24 1 2OE 1OE 48 25 1CLK 2CLK 47 36 D D 1D1 2D1 13 2 2O1 1O1 C C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MAY 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2775/13IDT74FCT163374A/C 3.3V CMOS 16-BIT REGISTER (3-STATE) INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V 1 48 1CLK (3) 1OE VTERM Terminal Voltage with Respect to GND 0.5 to 7 V (4) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 2 47 1O1 1D1 TSTG Storage Temperature 65 to +150 C 3 46 1O2 1D2 IOUT DC Output Current 60 to +60 mA GND 4 45 GND NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 5 44 1O3 1D3 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 6 43 1O4 1D4 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VCC 7 42 VCC 2. Vcc terminals. 3. Input terminals. 8 41 1O5 1D5 4. Outputs and I/O terminals. 9 40 1O6 1D6 GND 10 39 GND 11 38 1O7 1D7 CAPACITANCE (TA = +25C, F = 1.0MHz) (1) 12 37 Symbol Parameter Conditions Typ. Max. Unit 1O8 1D8 CIN Input Capacitance VIN = 0V 3.5 6 pF 13 36 2O1 2D1 COUT Output Capacitance VOUT = 0V 3.5 8 pF 14 35 2O2 2D2 NOTE: 1. This parameter is measured at characterization but not tested. GND GND 15 34 16 33 2O3 2D3 17 32 2O4 2D4 PIN DESCRIPTION VCC VCC Pin Names Description 18 31 x D x Data Inputs 19 30 2O5 2D5 xCLK Clock Inputs x O x 3-State Outputs 20 29 2O6 2D6 xOE 3-State Output Enable Input (Active LOW) GND 21 28 GND 22 27 2O7 2D7 23 26 2O8 2D8 24 25 2CLK 2OE (1) FUNCTION TABLE Inputs Outputs Function xDx xCLK xOE xOx Hi-Z X L H Z TOP VIEW XH H Z Package Type Package Code Order Code Load Register L LL TSSOP PAG48 PAG H LH SSOP PVG48 PVG L HZ H HZ NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High-Impedance = LOW-to-HIGH transition 2