74FCT162823ATPVG Renesas

IDT74FCT162823AT/CT FAST CMOS 18-BIT REGISTER INDUSTRIAL TEMPERATURE RANGE FAST CMOS 18-BIT IDT74FCT162823AT/CT REGISTER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT162823T 18-bit bus interface register is built using advanced, dual High-speed, low-power CMOS replacement for ABT functions metal CMOS technology. These high-speed, low-power registers with clock Typical tSK(o) (Output Skew) < 250ps enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing Low input and output leakage 1A (max.) in high-performance synchronous systems. The control inputs are organized VCC = 5V 10% to operate the device as two 9-bit registers or one 18-bit register. Flow-through Balanced Output Drivers of 24mA organization of signal pins simplifies layout. All inputs are designed with Reduced system switching noise hysteresis for improved noise margin. Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, The FCT162823T has balanced output drive with current limiting resistors. TA = 25C This offers low ground bounce, minimal undershoot, and controlled output fall Available in SSOP and TSSOP packages times reducing the need for external series terminating resistors. The FCT162823T is a plug-in replacement for the FCT16823T and ABT16823 for on-board interface applications. FUNCTIONAL BLOCK DIAGRAM 27 2 1OE 2OE 1 28 1CLR 2CLR 56 29 1CLK 2CLK 55 30 1CLKEN 2CLKEN R R C C 3 15 2Q1 1Q1 D D 54 42 1D1 2D1 TO EIGHT OTHER CHANNELS TO EIGHT OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 1 2009 Integrated Device Technology, Inc. DSC-5437/7IDT74FCT162823AT/CT FAST CMOS 18-BIT REGISTER INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to 7 V 1 56 1CLK 1CLR (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 2 55 1OE 1CLKEN TSTG Storage Temperature 65 to +150 C 3 54 IOUT DC Output Current 60 to +120 mA 1D1 1Q1 NOTES: GND 4 53 GND 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 5 52 permanent damage to the device. This is a stress rating only and functional operation 1D2 1Q2 of the device at these or any other conditions above those indicated in the operational 6 51 1D3 1Q3 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7 50 VCC VCC 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Outputs and I/O terminals for FCT162XXX. 8 49 1Q4 1D4 9 48 1Q5 1D5 10 47 1Q6 1D6 CAPACITANCE (TA = +25C, f = 1.0MHz) GND GND 11 46 (1) Symbol Parameter Conditions Typ. Max. Unit 12 45 1D7 CIN Input Capacitance VIN = 0V 3.5 6 pF 1Q7 COUT Output Capacitance VOUT = 0V 3.5 8 pF 13 44 1Q8 1D8 NOTE: 1Q9 14 43 1D9 1. This parameter is measured at characterization but not tested. 15 42 2Q1 2D1 16 41 2Q2 2D2 17 40 2D3 2Q3 PIN DESCRIPTION 18 39 GND GND Pin Names Description 19 38 x D x Data Inputs 2Q4 2D4 xCLK Clock Inputs 2Q5 20 37 2D5 xCLKEN Clock Enable Inputs (Active LOW) 2Q6 21 36 2D6 xCLR Asynchronous clear Inputs (Active LOW) VCC VCC 22 35 xOE Output Enable Inputs (ActiveLOW) 23 34 2Q7 2D7 x O x 3-State Outputs 24 33 2Q8 2D8 GND 25 32 GND (1)(1)(1) (1)(1) 26 31 2Q9 2D9 FUNCTION TABLE 27 30 2OE 2CLKEN Inputs Outputs xOE xCLR xCLKEN xCLK xDx xQx Function 2CLR 28 29 2CLK H X X X X Z High Z L L X X X L Clear SSOP/ TSSOP (2) TOP VIEW LH H X X Q Hold HH L L Z Load HH L HZ LH L LL LH L HH NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High-Impedance 2. Output level before indicated steady-state input conditions were established. 2