DATASHEET FN8340 TW2965 Rev. 1.00 Nov 21, 2013 4-CH WD1 (960H)/D1 Compatible Video Decoders and Audio Codecs with Video Encoder Features Video Decoder Audio Codecs WD1 (960H) and D1 compatible video decoding Integrated five audio ADCs processing and one operation and each channel is programmable audio DAC NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N Provides multi-channel audio mixed analog output combination), PAL (60) support with automatic Support I2S/DSP Master/Slave interface for format detection record output and playback input Software selectable analog inputs allows any of 2 PCM 8/16-bit and u-Law/A-Law 8-bit for audio CVBS per one video ADC word length Built-in analog anti-alias filter Programmable audio sample rate that covers popular frequencies of 8/16/32/44.1/48kHz Four 10-bit ADCs and analog clamping circuit for CVBS input Miscellaneous Fully programmable static gain or automatic gain control for the Y channel Two-wire MPU serial bus interface Programmable white peak control for CVBS Integrated clock PLL for 144/108MHz clock channel output 4-H adaptive comb filter Y/C separation Embedded video encoder PAL delay line for color phase error correction Power save and Power down mode Image enhancement with peaking and CTI Low power consumption Digital sub-carrier PLL for accurate color decoding Single 27MHz crystal for all standards and both Digital Horizontal PLL for synchronization WD1 and D1 format processing and pixel sampling 3.3V tolerant I/O Advanced synchronization processing and sync 1.0V/3.3V power supply detection for handling non-standard and weak 128-pin LQFP package signal Programmable hue, brightness, saturation, contrast, sharpness Automatic color control and color killer ITU-R 656 like YCbCr(4:2:2) output or time multiplexed output with 36/72/144MHz for WD1 or 27/54/108MHz for D1 format FN8340 Rev. 1.00 Page 1 of 130 Nov 21, 2013 TW2965 Function Description VIN1A VD1 7:0 44HH CCoommbb ADC ADC VViiddeeoo DDeeccooddeerr VD2 7:0 VIN1B VD3 7:0 AIN1 ADC ADC DDeecciimmaattiioonn FFiilltteerr VD4 7:0 MPP1 VIN2A MPP2 44HH CCoommbb ADC ADC VViiddeeoo DDeeccooddeerr MPP3 VIN2B MPP4 AIN2 AADDCC DDeecciimmaattiioonn FFiilltteerr CLKPO XTO VIN3A XTI 44HH CCoommbb AADDCC VViiddeeoo DDeeccooddeerr CLKNO VIN3B SCLK AIN3 AADDCC DDeecciimmaattiioonn FFiilltteerr SDAT IRQ VIN4A 44HH CCoommbb AADDCC ACLKR VViiddeeoo DDeeccooddeerr VIN4B ASYNR ADATR AIN4 ADC Decimation Filter ADC ADATM ACLKP ASYNP AIN5 Decimation Filter ADC ADATP DAC AOUT Interpolation Filter ENCLK Digital Video VYOUT DAC Encoder ED 7:0 FIGURE 1. TW2965 BLOCK DIAGRAM FN8340 Rev. 1.00 Page 2 of 130 Nov 21, 2013 MUX MUX MUX MUX Clock PLL I2S Host MPP BT.656 Clock Interface Interface Interface Interface Generator