DATASHEET FN7961 TW5864B1 Rev. 1.00 Jan 10, 2012 5D1 H264 Encoder with 4-Channel A/V Decoder and 12 Channel External VD Inputs for Security Applications The TW5864 is a H.264 encoder solution with support a total of 16 video input channels. The integrated 4-channel analog A/V decoders. video streams from both on-chip/off-chip video TW5864 can be used as a low cost single chip decoders are fed into H.264 encoder as well as to solution for 4-channel H.264 hardware external interfaces for preview purpose. The compression PC cards, or 16-channel cards by preview stream can go through either four BT. 656 using additional external TW2866 chips. There are video output interfaces or PCI interfaces. The four 3 versions of TW5864 that can support no BT 656 ports support both multi-channel byte or external video decoder (TW5864A), 4 channel line interleaved output to interface with various external video decoders (TW5864B), and 12 external display solutions. channel external video decoders (TW5864C). The TW5864 has built-in de-interlacers and OSDs TW5864 can also be used in embedded DVR before encoding is performed. There are also 16 applications as an AV front-end chip with H264 sets of motion detection / night detection / blind encoding capability. It can work with existing detection engine for channel alarm notification. In H.264 hardcore or DSP based CODECs. In existing addition, the hardware encoder generated motion H264 CODECs, performance may be limited due information of each channel is accessible to the to limitation in both memory bandwidth and external CPU for analytic purpose. TW5864 also hardware resources. With the H.264 encoder built integrates many sets of scalers for each of the in at the front-end, the number of encoding H264 encoder, MJPEG, and preview paths. Each of channel supported scales with number of these scalers is independently configured. TW5864 chips used. The front-end H264 encoder offloads the processing from the backend CODECs The TW5864 provides both asynchronous host to allow higher port count support and allows DSP interface and PCI interface for external CPU resources saved and reserved for product control and bitstream upload. The PCI interface differentiation features such as video analytic can run at 33 or 66 MHz. intelligence. Analog Video Decoder The TW5864 features H.264 baseline level 3 4 CVBS analog inputs fed into 4 sets of video compliant encoder capable of performing up to 5 decoder accept all NTSC(M/N/4.43) / PAL D1 equivalent video encoding (125 fps for PAL and 150 fps for NTSC), 17 channel G.726 ADPCM (B/D/G/H/I/K/L/M/N/60) standards with auto detection hardware audio encoder with one channel for two way audio communication. The H.264 video Integrated video analog anti-aliasing filters and encoder supports dual-bitstream compression for 10 bit CMOS ADCs for each video decoder both local storage and network port outputs. It High performance adaptive 4H comb filters for also features a motion JPEG encoder for up to 25 all NTSC/PAL standards frames per second shared among all video IF compensation filter for improvement of color channels. demodulation Color Transient Improvement (CTI) The TW5864 integrates 4 A/V decoders. It has 4 Automatic white peak control CVBS analog inputs fed into four internal high Programmable hue, saturation, contrast, quality NTSC/PAL video decoders. In addition, it brightness and sharpness has 3 digital BT. 656 input, running up to 108 Proprietary fast video locking system for non- MHz, capable of receiving up to 12 D1 video real-time application channels from external multi-channel video Noise Reduction to remove impulse noise decoders such as TW2866 / TW2867. This allows the TW5864 to Digital Input Ports Three BT. 656 ports, each running at 108 MHz, directly interfaced with 3 external TW2866s FN7961 Rev.1.00 Page 1 of 201 Jan 10, 2012 TW5864B1 Byte-interleaving supports 4 channels each port Host Interface Configurable 32-bit asynchronous host interface Interlaced D1 interface at 60 / 50 fields per / PCI interface second PCI Interface runs as both initiator and target at Progressive D1 interface at 30 / 25 frames 33 / 66 MHz per second Per channel night / blind detections Pre-processing Per channel de-interlacer to convert Interlaced Per channel triple high performance video into progressive before compression downscalers of each channel scales Per channel OSD for information overlay independently for H264, JPEG and preview Motion vector granularity at full pel, pel, and output pel Per channel motion detector with 16 X 12 cells Motion vector ranges -256, +255.75 Single Box In-loop de-blocking filter CAVLC entropy coding 1-bit per pixel text Video Analytic Interface 12-bit per pixel bitmap Per MB type / motion information Digital Output Ports 16x12 cells motion detection information Preview video for external display chips Accessible through PCI / Async Host Interface Four BT. 656 ports for preview raw video output Motion JPEG Encoder Byte-Interleaving interlaced D1 for all ports at 27 Maximum of 25 fps, shared among all channels or 108 MHz Support picture sizes of D1, CIF, and half-D1 Line-interleaving for the first 2 ports capable of supporting mix of interlaced D1 and CIF format Analog Audio CODEC at 27, 54, 81, or 108 MHz Integrated five audio ADCs and one audio DAC providing multi-channel audio mixed analog H.264 Video Encoder output H.264 baseline profile level 3 encoding Supports a standard I2S interface for record Bit rate from 64 kbps up to 10 mbps each output and playback input channel PCM 8/16 bit and u-Law/A-Law 8bit for audio Maximum 125 fps (PAL) or 150 fps (NTSC) word length Real-time 4 D1 / 16 CIF or non-real-time 16 D1 Programmable audio sample rate that covers main stream encoding popular frequencies of 8/16/32/44.1/48kHz Real-time 4 CIF / 16 QCIF or non-real-time 16 Video through PCI supporting various preview CIF secondary stream encoding resolution such as VBR / CBR controllable 2 D1 Configurable GOP interval 1 D1 + 4 CIF Digital Audio CODEC 9 CIF Hardware G.726 ADPCM encoder Encodes maximum of 17 channels, with 1 16 QCIF channel for two way communication 1 D1 + 15 QCIF Decodes 1 channel of audio for playback I2C Interface for external Video Decoder chips RTC for AV sync configuration DDR Interface IRQs and GPIOs Two 16-bit external DDR SDRAM memories System Clock Running at 166 MHz Single 27 MHz external crystal clock input Total 256 MB up to 1 GB 3 built-in PLLs for internal clock generation Auto refresh Package 352 BGA FN7961 Rev.1.00 Page 2 of 201 Jan 10, 2012