X4043, X4045 4k, 512 x 8 Bit Data Sheet March 16, 2006 FN8118.2 DESCRIPTION CPU Supervisor with 4kbit EEPROM The X4043/45 combines four popular functions, FEATURES Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial Selectable watchdog timer EEPROM Memory in one package. This combination Low V detection and reset assertion CC lowers system cost, reduces board space require- Five standard reset threshold voltages ments, and increases reliability. Adjust low V reset threshold voltage using CC special programming sequence Applying power to the device activates the power-on Reset signal valid to V = 1V CC reset circuit which holds RESET/RESET active for a Low power CMOS period of time. This allows the power supply and oscilla- <20A max standby current, watchdog on tor to stabilize before the processor can execute code. <1A standby current, watchdog OFF 3mA active current The Watchdog Timer provides an independent protec- 4kbits of EEPROM tion mechanism for microcontrollers. When the micro- 16-byte page write mode controller fails to restart a timer within a selectable Self-timed write cycle time out interval, the device activates the 5ms write cycle time (typical) RESET/RESET signal. The user selects the interval Built-in inadvertent write protection from three preset values. Once selected, the interval Power-up/power-down protection circuitry does not change, even after cycling the power. Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes The devices low V detection circuitry protects the CC of EEPROM array with Block Lock protection users system from low voltage conditions, resetting the 400kHz 2-wire interface system when V falls below the minimum V trip CC CC 2.7V to 5.5V power supply operation point. RESET/RESET is asserted until V returns to CC Available packages proper operating level and stabilizes. Five industry stan- 8 Ld SOIC dard V thresholds are available, however, Intersils TRIP 8 Ld MSOP unique circuits allow the threshold to be reprogrammed 8 Ld PDIP to meet custom requirements or to fine-tune the thresh- Pb-free plus anneal available (RoHS compliant) old for applications requiring higher precision. BLOCK DIAGRAM Watchdog Transition Watchdog Detector Timer Reset WP Protect Logic RESET (X4043) Data SDA RESET (X4045) Status Register Register Command EEPROM Array Reset & SCL Decode & Watchdog Control Timebase Logic V Threshold CC Reset logic Power-on and Low Voltage V + CC Reset V - Generation TRIP CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Block Lock Control 2Kbits 1Kb 1KbX4043, X4045 Ordering Information PART NUMBER RESET PART PART NUMBER PART V V TEMP CC TRIP (ACTIVE LOW) MARKING RESET (ACTIVE HIGH) MARKING RANGE (V) RANGE (V) RANGE (C) PACKAGE X4043S8-4.5A X4043 AL X4045S8-4.5A X4045 AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld SOIC X4043S8Z-4.5A (Note) X4043 Z AL X4045S8Z-4.5A (Note) X4045 Z AL 0 to 70 8 Ld SOIC (Pb-free) X4043S8I-4.5A X4043 AM X4045S8I-4.5A X4045 AM -40 to 85 8 Ld SOIC X4043S8IZ-4.5A (Note) X4043 Z AM X4045S8IZ-4.5A (Note) X4045 Z AM -40 to 85 8 Ld SOIC (Pb-free) X4043M8-4.5A ADA X4045M8-4.5A ADJ 0 to 70 8 Ld MSOP X4043M8Z-4.5A (Note) DAZ X4045M8Z-4.5A (Note) DBH 0 to 70 8 Ld MSOP (Pb-free) X4043M8I-4.5A ADB X4045M8I-4.5A ADK -40 to 85 8 Ld MSOP X4043M8IZ-4.5A (Note) DAU X4045M8IZ-4.5A (Note) DBE -40 to 85 8 Ld MSOP (Pb-free) X4043P-4.5A X4043P AL X4045P-4.5A X4045P AL 0 to 70 8 Ld PDIP X4043PZ-4.5A (Note) X4043P Z AL X4045PZ-4.5A (Note) X4045P Z AL 0 to 70 8 Ld PDIP (Pb-free) X4043PI-4.5A X4043P AM X4045PI-4.5A X4045P AM -40 to 85 8 Ld PDIP X4043PIZ-4.5A (Note) X4043P Z AM X4045PIZ-4.5A (Note) X4045P Z AM -40 to 85 8 Ld PDIP (Pb-free) X4043S8* X4043 X4045S8* X4045 4.5-5.5 4.25-4.5 0 to 70 8 Ld SOIC X4043S8Z* (Note) X4043 Z X4045S8Z* (Note) X4045 Z 0 to 70 8 Ld SOIC (Pb-free) X4043S8I* X4043 I X4045S8I X4045 I -40 to 85 8 Ld SOIC X4043S8IZ* (Note) X4043 Z I X4045S8IZ (Note) X4045 Z I -40 to 85 8 Ld SOIC (Pb-free) X4043M8 ADC X4045M8 ADL 0 to 70 8 Ld MSOP X4043M8Z* (Note) DAW X4045M8Z (Note) DBD 0 to 70 8 Ld MSOP (Pb-free) X4043M8I ADD X4045M8I ADM -40 to 85 8 Ld MSOP X4043M8IZ (Note) DAR X4045M8IZ (Note) DBA -40 to 85 8 Ld MSOP (Pb-free) X4043P X4043P Z X4045P X4045P 0 to 70 8 Ld PDIP X4043PZ (Note) X4043P X4045PZ (Note) X4045P Z 0 to 70 8 Ld PDIP (Pb-free) X4043PI X4043P I X4045PI X4045P I -40 to 85 8 Ld PDIP X4043PIZ (Note) X4043P Z I X4045PIZ (Note) X4045P Z I -40 to 85 8 Ld PDIP (Pb-free) X4043S8-2.7A* X4043 AN X4045S8-2.7A X4045 AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld SOIC X4043S8Z-2.7A* (Note) X4043 Z AN X4045S8Z-2.7A (Note) X4045 Z AN 0 to 70 8 Ld SOIC (Pb-free) X4043S8I-2.7A* X4043 AP X4045S8I-2.7A X4045 AP -40 to 85 8 Ld SOIC X4043S8IZ-2.7A* (Note) X4043 Z AP X4045S8IZ-2.7A (Note) X4045 Z AP -40 to 85 8 Ld SOIC (Pb-free) X4043M8-2.7A ADE X4045M8-2.7A AND 0 to 70 8 Ld MSOP X4043M8Z-2.7A (Note) DAY X4045M8Z-2.7A (Note) DBG 0 to 70 8 Ld MSOP (Pb-free) X4043M8I-2.7A ADF X4045M8I-2.7A ADO -40 to 85 8 Ld MSOP X4043M8IZ-2.7A (Note) DAT X4045M8IZ-2.7A (Note) DBC -40 to 85 8 Ld MSOP (Pb-free) X4043P-2.7A X4043P AN X4045P-2.7A X4045P AN 0 to 70 8 Ld PDIP X4043PZ-2.7A (Note) X4043P Z AN X4045PZ-2.7A (Note) X4045P Z AN 0 to 70 8 Ld PDIP (Pb-free) X4043PI-2.7A X4043P AP X4045PI-2.7A X4045P AP -40 to 85 8 Ld PDIP X4043PIZ-2.7A (Note) X4043P Z AP X4045PIZ-2.7A (Note) X4045P Z AP -40 to 85 8 Ld PDIP (Pb-free) FN8118.2 2 March 16, 2006