DATASHEET X5043, X5045 FN8126 Rev 3.00 4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM September 23, 2015 These devices combine four popular functions, Power-on Features Reset Control, Watchdog Timer, Supply Voltage Supervision, Low V Detection and Reset Assertion CC and Block Lock Protect Serial EEPROM Memory in one - Four standard reset threshold voltages package. This combination lowers system cost, reduces 4.63V, 4.38V, 2.93V, 2.63V board space requirements, and increases reliability. - Re-program low V reset threshold voltage using CC Applying power to the device activates the power-on reset special programming sequence. circuit which holds RESET/RESET active for a period of - Reset signal valid to V = 1V CC time. This allows the power supply and oscillator to stabilize Selectable Time Out Watchdog Timer before the processor executes code. Long Battery Life with Low Power Consumption The Watchdog Timer provides an independent protection - <50A max standby current, watchdog on mechanism for microcontrollers. When the microcontroller - <10A max standby current, watchdog off fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user 4Kbits of EEPROM1M Write Cycle Endurance selects the interval from three preset values. Once selected, Save Critical Data with Block Lock Memory the interval does not change, even after cycling the power. - Protect 1/4, 1/2, all or none of EEPROM array The devices low V detection circuitry protects the users CC Built-in Inadvertent Write Protection system from low voltage conditions, resetting the system - Write enable latch when V falls below the minimum V trip point. CC CC - Write protect pin RESET/RESET is asserted until V returns to proper CC operating level and stabilizes. Four industry standard V TRIP SPI Interface - 3.3MHz Clock Rate thresholds are available, however, Intersils unique circuits Minimize Programming Time allow the threshold to be reprogrammed to meet custom - 16-byte page write mode requirements or to fine-tune the threshold for applications - 5ms write cycle time (typical) requiring higher precision. Available Packages The memory portion of the device is a CMOS Serial - 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP EEPROM array with Intersils block lock protection. The - 14 Ld TSSOP array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol Pb-Free Plus Anneal Available (RoHS Compliant) allowing operation on a simple four-wire bus. Applications The device utilizes Intersils proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a Communications Equipment minimum data retention of 100 years. - Routers, Hubs, Switches - Set Top Boxes Industrial Systems - Process Control - Intelligent Instrumentation Computer Systems - Desktop Computers - Network Servers Battery Powered Equipment FN8126 Rev 3.00 Page 1 of 21 September 23, 2015X5043, X5045 Typical Application 2.7-5.0V VCC uC VCC 10K X5043 RESET RESET CS SCK SPI SI SO WP VSS VSS Block Diagram POR and Low RESET (X5043) V + Voltage Reset CC RESET (X5045) Generation V - TRIP Reset & Watchdog X5043, X5045 Timebase STANDARD V LEVEL SUFFIX TRIP Watchdog Watchdog 4.63V (+/-2.5%) -4.5A Timer Transition Detector Reset 4.38V (+/-2.5%) -4.5 2.93V (+/-2.5%) -2.7A CS/WDI Status Command Register 2.63V (+/-2.5%) -2.7 SI Decode & SO Control See Ordering Information on page 3. for EEPROM Logic more details SCK Array For Custom Settings, call Intersil. 4Kbits WP Protect Logic FN8126 Rev 3.00 Page 2 of 21 September 23, 2015