X9250US24Z-2.7 Renesas

DATASHEET X9250 FN8165 Rev.3.00 Low Noise/Low Power/SPI Bus/256 Taps Quad Digitally Controlled August 29, 2006 Potentiometers (XDCP) FEATURES DESCRIPTION Four potentiometers in one package The X9250 integrates 4 digitally controlled 256 resistor taps/pot - 0.4% resolution potentiometers (XDCP) on a monolithic CMOS SPI serial interface integrated circuit. Wiper resistance, 40 typical V = 5V CC The digitally controlled potentiometer is implemented Four nonvolatile data registers for each pot using 255 resistive elements in a series array. Nonvolatile storage of wiper position Between each element are tap points connected to the Standby current < 5A max (total package) wiper terminal through switches. The position of the Power supplies wiper on the array is controlled by the user through the V = 2.7V to 5.5V CC SPI bus interface. Each potentiometer has associated V+ = 2.7V to 5.5V with it a volatile Wiper Counter Register (WCR) and 4 V = -2.7V to -5.5V nonvolatile Data Registers (DR0:DR3) that can be 100k, 50k total pot resistance directly written to and read by the user. The contents High reliability of the WCR controls the position of the wiper on the Endurance 100,000 data changes per bit per resistor array though the switches. Power up recalls register the contents of DR0 to the WCR. Register data retention - 100 years 24 Ld SOIC, 24 Ld TSSOP The XDCP can be used as a three-terminal Dual supply version of X9251 potentiometer or as a two-terminal variable resistor in Pb-free plus anneal available (RoHS compliant) a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM V V+ CC Pot 0 V V- SS R R V /R R R 0 1 H0 H0 0 1 Wiper Wiper V /R H2 H2 Resistor Counter Counter Array Register Register Pot 2 (WCR) (WCR) V /R R R L0 L0 HOLD R R 2 3 2 3 V /R L2 L2 CS V /R W0 W0 V /R W2 W2 SCK Interface SO and SI Control 8 Circuitry A0 V /R A1 W1 W1 Data V /R W3 W3 WP R R 0 1 R R Wiper V /R 0 1 H1 H1 V /R Wiper H3 H3 Resistor Counter Resistor Counter Array Register Array Register Pot1 (WCR) Pot 3 R R (WCR) 2 3 V /R R R L1 L1 2 3 V /R L3 H3 FN8165 Rev.3.00 Page 1 of 20 August 29, 2006X9250 Ordering Information PART POTENTIOMETER TEMP. RANGE PART NUMBER MARKING V LIMITS (V) ORGANIZATION (k) (C) PACKAGE PKG. DWG. CC X9250TS24I X9250TS I 5 10% 100 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250TS24IZ (Note) X9250TS ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9250TV24I X9250TV I -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) X9250TV24IZ (Note) X9250TV ZI -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) (Pb-free) X9250US24 X9250US 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250US24Z (Note) X9250US Z 0 to +70 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9250US24I X9250US I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250US24IZ (Note) X9250US ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9250UV24I X9250UV I -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) X9250UV24IZ (Note) X9250UV ZI -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) (Pb-free) X9250TS24-2.7 X9250TS F -2.7 to 5.5 100 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250TS24Z-2.7 (Note) X9250TS ZF 0 to +70 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9250TS24I-2.7* X9250TS G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250TS24IZ-2.7* X9250TS ZG -40 to +85 24 Ld SOIC (300 mil) M24.3 (Note) (Pb-free) X9250TV24I-2.7 X9250TV G -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) X9250TV24IZ-2.7 (Note) X9250TV ZG -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) (Pb-free) X9250US24-2.7* X9250US F 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9250US24Z-2.7* (Note) X9250US ZF 0 to +70 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9250US24I-2.7 X9250US G -40 to +85 24 Ld SOIC (300 mil) M24.3 X9250US24IZ-2.7 (Note) X9250US ZG -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9250UV24-2.7 X9250UV F 0 to +70 24 Ld TSSOP MDP0044 (4.4mm) X9250UV24Z-2.7 (Note) X9250UV ZF 0 to +70 24 Ld TSSOP MDP0044 (4.4mm) (Pb-free) X9250UV24I-2.7 X9250UV G -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) X9250UV24IZ-2.7 (Note) X9250UV ZG -40 to +85 24 Ld TSSOP MDP0044 (4.4mm) (Pb-free) *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8165 Rev.3.00 Page 2 of 20 August 29, 2006