DATASHEET X9268 FN8172 Rev.4.00 Dual Supply/Low Power/256-Tap/2-Wire Bus Dual Digitally-Controlled (XDCP) August 29, 2006 Potentiometers FEATURES DESCRIPTION DualTwo Separate Potentiometers The X9268 integrates 2 digitally controlled 256 Resistor Taps/Pot0.4% Resolution potentiometer (XDCP) on a monolithic CMOS 2-Wire Serial Interface for Write, Read, and integrated circuit. Transfer Operations of the Potentiometer The digital controlled potentiometer is implemented Wiper Resistance, 100 typical V+ = 5V, using 255 resistive elements in a series array. V- = -5V Between each element are tap points connected to the 16 Nonvolatile Data Registers for Each wiper terminal through switches. The position of the Potentiometer wiper on the array is controlled by the user through the Nonvolatile Storage of Multiple Wiper Positions 2-Wire bus interface. Each potentiometer has Power-on Recall. Loads Saved Wiper Position on associated with it a volatile Wiper Counter Register Power-up. (WCR) and a four nonvolatile Data Registers that can Standby Current <5A Max be directly written to and read by the user. The V : 2.7V to 5.5V Operation CC contents of the WCR controls the position of the wiper 50k , 100k Versions of End to End Pot on the resistor array though the switches. Powerup Resistance recalls the contents of the default Data Register (DR0) Endurance: 100,000 Data Changes per Bit per to the WCR. Register 100 yr. Data Retention The XDCP can be used as a three-terminal 24 Ld SOIC potentiometer or as a two terminal variable resistor in Low Power CMOS a wide variety of applications including control, Power Supply V = 2.7V to 5.5V CC parameter adjustments, and signal processing. V+ = 2.7V to 5.5V V- = -2.7V to -5.5V Pb-Free Plus Anneal Available (RoHS Compliant) FUNCTIONAL DIAGRAM V R R CC V H0 H1 + Write Read Address Transfer Power-on Recall Data Inc/Dec Status Bus 2-Wire Wiper Counter Bus Interface Registers (WCR) Interface and Control Data Registers (DR0DR3) Control V V- R R R R SS W0 L0 W1 L1 50k or 100k versions FN8172 Rev.4.00 Page 1 of 22 August 29, 2006X9268 Ordering Information PART V LIMITS POTENTIOMETER TEMP. RANGE PKG. CC PART NUMBER MARKING (V) ORGANIZATION (k ) (C) PACKAGE DWG. X9268TS24 X9268TS 5 10% 100 0 to +70 24 Ld SOIC (300mil) M24.3 X9268TS24Z (Note) X9268TS Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268TS24I X9268TS I -40 to +85 24 Ld SOIC (300mil) M24.3 X9268TS24IZ (Note) X9268TS ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268US24 X9268US 50 0 to +70 24 Ld SOIC (300mil) M24.3 X9268US24Z (Note) X9268US Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268US24I X9268US I -40 to +85 24 Ld SOIC (300mil) M24.3 X9268US24IZ (Note) X9268US ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3 X9268TS24I-2.7 X9268TS G 2.7 to 5.5 100 -40 to +85 24 Ld SOIC (300mil) M24.3 X9268TS24IZ-2.7 (Note) X9268TS ZG -40 to +85 24 Ld SOIC (300mil) (Pb-Free) M24.3 *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8172 Rev.4.00 Page 2 of 22 August 29, 2006