DATASHEET X95820 FN8212 2 Rev 2.00 Dual Digital Controlled Potentiometers (XDCP) Low Noise/Low Power/I C July 18, 2006 Bus/256 Taps The X95820 integrates two digitally controlled Features potentiometers (XDCP) on a monolithic CMOS integrated Two potentiometers in one package circuit. 256 resistor taps-0.4% resolution The digitally controlled potentiometers are implemented with 2 a combination of resistor elements and CMOS switches. The I C serial interface position of the wipers are controlled by the user through the - Three address pins, up to eight devices/bus 2 I C bus interface. Each potentiometer has an associated Wiper resistance: 70 typical 3.3V volatile Wiper Register (WR) and a non-volatile Initial Value Non-volatile storage of wiper position Register (IVR), that can be directly written to and read by the user. The contents of the WR controls the position of the Standby current < 5A max wiper. At power up the device recalls the contents of the two Power supply: 2.7V to 5.5V DCPs IVR to the corresponding WRs. 50k, 10k total resistance The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of High reliability applications including control, parameter adjustments, and - Endurance: 150,000 data changes per bit per register signal processing. - Register data retention: 50 years T 75C 14 Ld TSSOP Ordering Information Pb-free plus anneal available (RoHS compliant) PART RESISTANCE PART NUMBER MARKING OPTION PACKAGE Pinouts X95820WV14I-2.7* X95820WV G 10k 14 Ld TSSOP X95820 X95820WV14IZ-2.7* X95820WV Z G 10k 14 Ld TSSOP (14 LD TSSOP) (Note) (Pb-free) TOP VIEW X95820UV14I-2.7* X95820UV G 50k 14 Ld TSSOP V CC 14 1 A1 X95820UV14IZ-2.7* X95820UV Z G 50k 14 Ld TSSOP WP A0 2 13 (Note) (Pb-free) RH0 RH1 3 12 RL0 *AddT1 suffix for tape and reel. 11 4 RL1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free RW0 RW1 5 10 material sets molding compounds/die attach materials and 100% A2 9 GND 6 matte tin plate termination finish, which are RoHS compliant and SCL SDA 7 8 compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8212 Rev 2.00 Page 1 of 12 July 18, 2006X95820 Block Diagram V CC 2 R I C H1 POWER-UP, INTERFACE INTERFACE, R WR1 W1 SDA CONTROL AND SCL STATUS LOGIC R L1 A2 R A1 H0 A0 R WR0 W0 NON-VOLATILE REGISTERS R L0 WP GND PiN Descriptions PIN SYMBOL DESCRIPTION 1V Power supply pin CC 2 2WP Hardware write protection pin. Active low. Prevents any Write operation of the I C interface. 3 RH0 High terminal of DCP0 4 RL0 Low terminal of DCP0 5 RW0 Wiper terminal of DCP0 2 6 A2 Device address for the I C interface 2 7SCLI C interface clock 2 8 SDA Serial data I/O for the I C interface 9 GND Ground 10 RW1 Wiper terminal of DCP1 11 RL1 Low terminal of DCP1 12 RH1 High terminal of DCP1 2 13 A0 Device address for the I C interface 2 14 A1 Device address for the I C interface FN8212 Rev 2.00 Page 2 of 12 July 18, 2006