DATASHEET X95840 FN8213 2 Rev 2.00 Quad Digital Controlled Potentiometers (XDCP) Low Noise/Low Power/I C July 5, 2006 Bus/256 Taps The X95840 integrates four digitally controlled Features potentiometers (XDCP) on a monolithic CMOS integrated Four Potentiometers in One Package circuit. 256 Resistor Taps-0.4% Resolution The digitally controlled potentiometers are implemented with 2 a combination of resistor elements and CMOS switches. The I C Serial Interface position of the wipers are controlled by the user through the - Three address pins, up to eight devices/bus 2 I C bus interface. Each potentiometer has an associated Wiper Resistance: 70 Typical 3.3V volatile Wiper Register (WR) and a non-volatile Initial Value Non-Volatile Storage of Wiper Position Register (IVR), that can be directly written to and read by the user. The contents of the WR controls the position of the Standby Current < 5A Max wiper. At power up the device recalls the contents of the four Power Supply: 2.7V to 5.5V DCPs IVR to the corresponding WRs. 50k, 10k Total Resistance The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of High Reliability applications including control, parameter adjustments, and - Endurance: 150,000 data changes per bit per register signal processing. - Register data retention: 50 years T 75C 20 Ld TSSOP Ordering Information Pb-Free Plus Anneal Available (RoHS Compliant) PART RESISTANCE PART NUMBER MARKING OPTION PACKAGE Pinouts X95840WV20I-2.7* X95840WV G 10k 20 Ld TSSOP X95840 X95840WV20IZ-2.7* X95840WV Z G 10k 20 Ld TSSOP (20 LD TSSOP) (Note) (Pb-free) TOP VIEW X95840UV20I-2.7* X95840UV G 50k 20 Ld TSSOP RH3 1 20 RW0 X95840UV20IZ-2.7* X95840UV Z G 50k 20 Ld TSSOP RL3 2 RL0 19 (Note) (Pb-free) RW3 3 18 RH0 *Add T1 suffix for tape and reel. WP A2 4 17 5 V SCL 16 CC NOTE: Intersil Pb-free plus anneal products employ special Pb-free SDA A1 material sets molding compounds/die attach materials and 100% 6 15 matte tin plate termination finish, which are RoHS compliant and GND 7 A0 14 compatible with both SnPb and Pb-free soldering operations. Intersil 8 RW2 13 RH1 Pb-free products are MSL classified at Pb-free peak reflow 9 RL2 12 RL1 temperatures that meet or exceed the Pb-free requirements of RH2 10 IPC/JEDEC J STD-020. 11 RW1 FN8213 Rev 2.00 Page 1 of 13 July 5, 2006X95840 Block Diagram V CC R H3 2 WR3 R DCP3 W3 I C POWER-UP, R L3 INTERFACE INTERFACE, SDA CONTROL AND SCL StAtus LOGIC R H2 R WR2 DCP2 W2 R L2 A2 R H1 A1 R WR1 DCP1 W1 R L1 A0 NON-VOLATILE REGISTERS R H0 R WR0 DCP0 W0 R L0 WP GND Pin Descriptions TSSOP PIN SYMBOL DESCRIPTION 1 RH3 High terminal of DCP3 2 RL3 Low terminal of DCP3 3 RW3 Wiper terminal of DCP3 2 4 A2 Device address for the I C interface 2 5SCLI C interface clock 2 6 SDA Serial data I/O for the I C interface 7 GND Device ground pin 8 RW2 Wiper terminal of DCP2 9 RL2 Low terminal of DCP2 10 RH2 High terminal of DCP2 11 RW1 Wiper terminal of DCP1 12 RL1 Low terminal of DCP1 13 RH1 High terminal of DCP1 2 14 A0 Device address for the I C interface 2 15 A1 Device address for the I C interface 16 V Power supply pin CC 2 17 WP Hardware write protection pin. Active low. Prevents any Write operation of the I C interface. 18 RH0 High terminal of DCP0 19 RL0 Low terminal of DCP0 20 RW0 Wiper terminal of DCP0 FN8213 Rev 2.00 Page 2 of 13 July 5, 2006