DATASHEET X9400 FN8189 Rev 4.00 Low Noise/Low Power/SPI Bus Quad Digitally Controlled Potentiometers September 2, 2015 (XDCP) FEATURES DESCRIPTION Four potentiometers per package The X9400 integrates four digitally controlled 64 resistor taps potentiometers (XDCPs) on a monolithic CMOS SPI serial interface for write, read, and transfer integrated circuit. operations of the potentiometer The digitally controlled potentiometer is implemented Wiper resistance, 40 typical at 5V. using 63 resistive elements in a series array. Between Four non-volatile data registers for each each element are tap points connected to the wiper potentiometer terminal through switches. The position of the wiper on Non-volatile storage of multiple wiper position the array is controlled by the user through the SPI Power-on recall. Loads saved wiper position on serial bus interface. Each potentiometer has power-up. associated with it a volatile Wiper Counter Register Standby current < 1A max (WCR) and four nonvolatile Data Registers (DR0-3) System V : 2.7V to 5.5V operation CC that can be directly written to and read by the user. + Analog V /V : -5V to +5V The contents of the WCR controls the position of the 10k , 2.5k end to end resistance wiper on the resistor array through the switches. 100 yr. data retention Power-up recalls the contents of DR0 to the WCR. Endurance: 100,000 data changes per bit per register The XDCP can be used as a three-terminal Low power CMOS potentiometer or as a two-terminal variable resistor in 24 Ld SOIC and 24 Ld TSSOP a wide variety of applications including control, Pb-free plus anneal available (RoHS compliant) parameter adjustments, and signal processing. BLOCK DIAGRAM V CC Pot 0 V SS R0 R1 V /R R0 R1 H0 H0 V+ Wiper Wiper V /R H2 H2 Resistor V- Counter Counter Array Register Register Pot 2 (WCR) (WCR) V /R R2 R3 L0 L0 R2 R3 HOLD V /R L2 L2 CS V /R W0 W0 V /R W2 W2 SCK Interface SO and SI Control 8 Circuitry A0 A1 V /R W1 W1 Data V /R W3 W3 WP R0 R1 R0 R1 Wiper V /R H1 H1 Resistor Wiper V /R H3 H3 Counter Resistor Array Counter Register Array Pot 1 Register (WCR) Pot 3 R2 R3 (WCR) V /R R2 R3 L1 L1 V /R L3 L3 FN8189 Rev 4.00 Page 1 of 20 September 2, 2015X9400 Ordering Information V POTENTIOMETER TEMP. CC PART LIMITS ORGANIZATION RANGE PKG. PART NUMBER MARKING (V) (k ) (C) PACKAGE DWG. X9400WS24ZT1 (Note) (No longer available, X9400WS Z 5 10% 10 0 to +70 24 Ld SOIC (300 mil) M24.3 recommended replacement: X9400WS24IZT1) (Pb-free) Tape and Reel X9400WS24IZ* (Note) X9400WS ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9400WV24IZ* (Note) X9400WV ZI -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 (Pb-free) X9400WV24Z* (Note) (No longer available, X9400WV Z 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 recommended replacement: X9400WS24IZT1) (Pb-free) X9400WS24IZ-2.7* (Note) X9400WS ZG 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9400WV24IZ-2.7* (Note) (No longer available, X9400WV ZG -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 recommended replacement: X9400WS24IZT1) (Pb-free) X9400WV24Z-2.7* (Note) (No longer available, X9400WV ZF 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 recommended replacement: X9400WS24IZT1) (Pb-free) *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8189 Rev 4.00 Page 2 of 20 September 2, 2015