ZL2105ALNFT1 Renesas

NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED ZL2105 REPLACEMENT PART ZL2102 Data Sheet March 30, 2011 FN6851.2 3A Integrated Digital DC-DC Converter Description Features Power Conversion The ZL2105 is an innovative power conversion and High efficiency management IC that combines an integrated 3 A continuous output current synchronous step-down DC-DC converter with key Integrated MOSFET switches power management functions in a small package, 4.5 V to 14 V input range resulting in a flexible and integrated solution. 0.54 V to 5.5 V output range (with margin) Zilker Labs Digital-DC technology enables 1% output voltage accuracy unparalleled power management integration while 200 kHz to 2 MHz switching frequency delivering industry-leading performance in a tiny Supports phase spreading footprint. Small footprint (6 x 6 mm QFN package) The ZL2105 can provide an output voltage from Power Management 0.6 V to 5.5 V from an input voltage between 4.5 V Digital soft start/stop and 14 V. Internal 4.5 A low R synchronous Precision delay and ramp-up DS(ON) power MOSFETs enable the ZL2105 to deliver Power good/enable continuous loads up to 3 A with high efficiency, Voltage tracking, sequencing, and margining and an internal Schottky bootstrap diode further Output voltage/current monitoring reduces discrete component count. The ZL2105 Thermal monitor w/ shutdown Non-volatile memory also supports phase spreading for reduced system 2 I C/SMBus communication bus capacitance. PMBus compatible Power management features such as digital soft- start delay and ramp, sequencing, tracking, and Applications margining can be configured by simple pin- Telecom and storage equipment strapping or through an on-chip serial port. The Digital set-top box ZL2105 uses standard PMBus protocol for Industrial supplies communicating with other devices to provide 12 V distributed power systems intelligent system power management. Point of load converters V IN Temp 2.5V 5V BST EN Sense LDO LDO SYNC CFG MGN PWM Power TRK SW Control Mgmt UVLO DLY V & OUT SW SS Drivers V0 NVM VSEN V1 PG Chg SA SMBus Pump Figure 1. Block Diagram 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. 1 Copyright Intersil Americas Inc. 2009, 2013. All Rights Reserved All other trademarks mentioned are the property of their respective owners XTEMP SDA SCL SALRT 2V5 VDDL VDR VRA CP1 VR CP2 PGND VDDS VDDP PGND VDDPZL2105 Table of Contents 1. Electrical Characteristics ............................................................................................................................................... 3 2. Pin Descriptions ............................................................................................................................................................ 6 3. Typical Application Circuit ........................................................................................................................................... 8 4. ZL2105 Overview ....................................................................................................................................................... 10 4.1 Digital-DC Architecture ........................................................................................................................................ 10 4.2 Power Conversion Overview ................................................................................................................................ 11 4.3 Power Management Overview .............................................................................................................................. 12 4.4 Multi-mode Pins .................................................................................................................................................... 12 5. Power Conversion Functional Description .................................................................................................................. 13 5.1 Internal Bias Regulators and Input Supply Connections ...................................................................................... 13 5.2 High-side Driver Boost Circuit ............................................................................................................................. 13 5.3 Low-side Driver Supply Options .......................................................................................................................... 13 5.4 Dual Input Supply Configuration .......................................................................................................................... 14 5.5 Output voltage Selection ....................................................................................................................................... 15 5.6 Start-up Procedure ................................................................................................................................................. 15 5.7 Soft Start Delay and Ramp Times ......................................................................................................................... 16 5.8 Switching Frequency and PLL .............................................................................................................................. 17 5.9 Component Selection ............................................................................................................................................ 19 5.10 Current Sensing and Current Limit Threshold Selection .................................................................................... 22 5.11 Loop Compensation ............................................................................................................................................ 22 5.12 Non-linear Response (NLR) Settings .................................................................................................................. 23 5.13 Efficiency Optimized Drive Dead-time Control ................................................................................................. 24 6. Power Management Functional Description ............................................................................................................... 24 6.1 Input Undervoltage Lockout ................................................................................................................................. 24 6.2 Power Good (PG) and Output Overvoltage Protection ......................................................................................... 25 6.3 Output Overvoltage Protection ............................................................................................................................. 25 6.4 Output Pre-Bias Protection ................................................................................................................................... 25 6.5 Output Overcurrent Protection .............................................................................................................................. 26 6.6 Thermal Overload Protection ................................................................................................................................ 26 6.7 Voltage Tracking................................................................................................................................................... 27 6.8 Voltage Margining ................................................................................................................................................ 28 2 6.9 I C/SMBus Communications ................................................................................................................................ 29 2 6.10 I C/SMBus Device Address Selection ................................................................................................................ 29 6.11 Phase Spreading .................................................................................................................................................. 29 6.12 Output Sequencing .............................................................................................................................................. 30 2 6.13 Monitoring via I C/SMBus ................................................................................................................................. 31 6.14 Temperature Monitoring using the XTEMP Pin ................................................................................................. 31 6.15 Non-Volatile Memory and Device Security Features ......................................................................................... 32 7. Package Dimensions .................................................................................................................................................... 33 8. Ordering Information .................................................................................................................................................. 34 9. Related Documentation ............................................................................................................................................... 34 10. Revision History ........................................................................................................................................................ 35 FN6851.2 2 March 30, 2011