USERS MANUAL ZL9101EVAL1Z AN1625 Rev 0.00 Digital DC/DC 12A Module Evaluation Board February 4, 2011 Description Key Features The ZL9101M is a 12A variable output, step-down power Complete Switch Mode Power Supply supply module. Included in the module is a high-performance 12A DC Output Current digital PWM controller, power MOSFETs, an inductor, and all Adjustable +0.6V to +4V Output Range the passive components required for a complete DC/DC power Up to 90% Efficiency solution. The ZL9101M operates over a wide input voltage range and supports an output voltage range of 0.6V to 4V, Digital Control PWM which can be set by external resistors or via the PMBus. This Fixed 615kHz Switching Frequency high-efficiency power module is capable of delivering 12A. Fast Transient Response Only bulk input and output capacitors are needed to finish the Enable Function Option design. The output voltage can be precisely regulated to as low as 0.6V with 1% output voltage regulation. Power-Good Indicator The ZL9101EVAL1Z is a 6-layer board that provides a Convenient Power Connection single-phase power rail up to 12A loads. The board is designed Multiple Power Options to efficiently transfer heat away from the module with passive Single Supply Operation cooling. Configurable Through SMBus A USB to SMBus adapter is used to connect the ZL9101EVAL1Z board to a PC. The PMBus command set is accessed by using the PowerNavigator evaluation software. Key Specifications The ZL9101EVAL1Z has been designed and optimized for the following parameters: V = 12V IN V = 1.2V OUT I = 15A OUT(MAX) F = 615kHz SW V < 1% OUT(RIPPLE) Transient Response = 3% (3A to 9A step at 2.5V/s) P4 P3 P2 J11 VIN VDRV Linear J8 J9 Regulator VDD J10 PG 0 ZL9101M 3 2 Thermal 1 Connection SW2 JP1 P1 ZL 9101 ZL1505 HW EN VDD VDD EN EN PG PG PWMH PWMH GH SYNC SW SYNC PWML PWML SCL SCL SDA VOUT SDA SW DDC DDC ISENA VTRK VTRK ISENB SA0 V1 GL V25 FB- VR FB+ GND J4 J5 SGND A ddress Voltage SG PGND J2 Pinstra p Pinstrap FB- FB+ FIGURE 1. ZL9101EVAL1Z EVALUATION BOARD BLOCK DIAGRAM AN1625 Rev 0.00 Page 1 of 12 February 4, 2011ZL9101EVAL1Z PowerNavigator or load a predefined scenario from a Functional Description configuration file. The ZL9101EVAL1Z evaluation board provides all the circuitry The ENABLE switch can then be moved to ENABLE and the required to evaluate the features of the ZL9101M module. The ZL9101M can be tested. Alternately, the PMBus ONOFF, CONFIG, ZL9101EVAL1Z has a performance-optimized, single-phase and OPERATION commands can be used. ZL9101M circuit layout that allows operation up to the maximum rated output current. Power options and load connections are Single-Supply Operation provided through plug-in sockets and shorting jumpers. The ZL9101EVAL1Z board was designed to facilitate operation Figure 1 shows a functional block diagram of the ZL9101EVAL1Z from a single power supply input. The single input power mode board. The SMBus address is selectable through J4 located on reduces the number of connections but results in a minor 2 and I C bus) the top side of the board. All power to the board (V IN reduction of efficiency. must be removed before changing the jumpers. The driver bias is supplied by an onboard linear regulator. The hardware enable function is controlled by a toggle switch on Figure 3 shows the onboard regulator circuit for powering the the ZL9101EVAL1Z board. The power-good (PG) LED indicates ZL9101M driver. Jumpers J8 and J9 connect the supply power to the state of PG when external power is applied to the the linear regulator that is used to power the driver, and J6 ZL9101EVAL1Z board. The right-angle headers at opposite ends connects input power to the ZL9101M digital module. If of the board are for connecting a USB to an SMBus adapter board single-supply operation is desired, J6, J8, and J9 must be or for daisy-chaining of multiple evaluation boards. installed. Figure 2 shows the ZL9101EVAL1Z operational circuit. The circuit consists of the ZL9101M module and supporting components. Multi-Supply Operation (External Driver Figure 3 shows the ZL9101EVAL1Z interface schematic. Supply) Figures 4 through 9 show the layers of the ZL9101EVAL1Z To operate the ZL9101EVAL1Z driver from an external power evaluation board. supply, remove J8 and J9, and connect an external power supply to the driver connector, P3, between 4.5V to 6.5V. Basic Operation To operate the ZL9101EVAL1Z board using different power The ZL9101EVAL1Z evaluation board is easy to set up and supplies for the controller and FETs, remove J6 and apply an operate. It is optimally configured, out of the box, to provide 1.2V external power supply to power the FETs to P4 to between 3.0V at 12A from a 12V source. All input and output connections and 14V. should be made before applying power. Apply a power supply voltage to the ZL9101M module through The ZL9101M module requires a configuration file in order to the P2 connector. operate. The ZL9101M supports pinstrap configuration for output voltage is 4.5V V 5.5V, then apply 4.5V to 5.5V to If the V DD DD voltage and SMBus address. All other parameters must be P2, and connect V to V . Do not exceed 5.5V while V is R DD R configured with a text-based configuration file. See application connected to V or permanent damage will result. DD note AN2031 for more information on writing configuration files. If the V voltage is 5.5V V 14V, then apply 5.5V to 14V to An example configuration file is listed at the end of this DD DD P2, and do not connect to V . document. R The ZL9101EVAL1Z comes configured to use hardware Enable. Pinstraps Toggle the power switch to the Enable position to power on. Use the GUI to change the configuration, if desired. The ZL9101M requires a configuration file for normal operation however, there are two pinstrap functions to be configured: Power Good Voltage and SMBus address. Ensure that input power is removed, and then set the address and voltage pinstraps using J4 and J6. The ZL9101M provides a Power-Good (PG) signal, which indicates Apply V power, and the new settings will be in effect. that the output voltage is within a specified tolerance of its target DD level and that no fault condition exists. By default, the PG pin PMBus Operation asserts if the output is within 10% of the target voltage. These limits and the polarity of the pin may be changed via the The ZL9101M utilizes the PMBus protocol. The PMBus 2 C/SMBus interface. See Application Note AN2033 for details. I functionality can be controlled via USB from a PC running the PowerNavigator evaluation software in a Windows XP or A PG delay period is defined as the time from when all conditions Windows 2000/NT operating system. within the ZL9101M for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of Install the PowerNavigator software using the CD included in using an external reset controller to control external digital logic. the ZL9101EVAL1Z kit. For PMBus operation, connect the USB-to- By default, the ZL9101M PG delay is set equal to the soft-start SMBus dongle board to J7 of the ZL9101EVAL1Z board. Connect ramp time setting of 10ms. The PG delay may be set the desired load and an appropriate power supply to the input. 2 independently of the soft-start ramp by using the I C/SMBus as Place the ENABLE switch in DISABLE and turn on the power. described in Application Note AN2033. The PowerNavigator evaluation software allows modification of all ZL9101M PMBus parameters. See Application Note AN2033 for PMBus command details. Use the mouse-over pop-ups for PowerNavigator help. Manually configure the ZL9101M through AN1625 Rev 0.00 Page 2 of 12 February 4, 2011