1/4 Structure Silicon monolithic integrated circuit Product Name System LSI for Event data recorder Type BU1511KV2 Function BU1511KV2 is a system LSI for event data recorder that makes developing it easier BU1511KV2 have built-in specific hardware to communicate and control with a 3-axis accelerometer and a camera module, SD card, etc. that are recommended for event data recorder. The specific hardware are controllerable by built-in ARM946E-S, which can execute various applications. The following function blocks are built-in. ARM946E-S Interrupt Controller External Memory Interface Timer/Timer Counter GPIO(16ch, PWM 4ch(shared), IRQ 4ch(shared)) UART(2ch) SD Card Interface/SD Card Controller I2C Master Controller SSI(Synchronous Serial Interface) Camera Interface (up to 2M pixels) Watch Dog Timer JPEG Codec ADPCM Audio Codec with IIS Interface Clock Controller/PLL TV Encoder(within 75 driver) A/D Converter(4ch) Absolute maximum ratings Parameter Symbol Rating Unit Parameter Symbol Rating Unit Power supply voltage 1 (DAC) DAVDD -0.3+4.2 V Input voltageADC VIN1 -0.3ADVDD+0.3 V Power supply voltage 2 (ADC) ADVDD -0.3+4.2 V Input voltageI2C-1 VIN2 -0.3I1VDD+0.3 V Power supply voltage 3 (I2C-1) I1VDD -0.3+4.2 V Input voltageI2C-2 VIN3 -0.3I2VDD+0.3 V Power supply voltage 4 (I2C-2) I2VDD -0.3+4.2 V Input voltageSD-CARD VIN4 -0.3SDVDD+0.3 V Power supply voltage 5 (SD-CARD) SDVDD -0.3+4.2 V Input voltageCAMERA VIN5 -0.3CAVDD+0.3 V Power supply voltage 6(CAMERA) CAVDD -0.3+4.2 V Input voltageOther IO VIN6 -0.3IOVDD+0.3 V Power supply voltage 7(Other IO) IOVDD -0.3+4.2 V Storage temperature range Tstg -40+150 C Power supply voltage 8(Digital CORE) DVDD -0.3+2.1 V Power dissipation PD 1200*1, 1700*2 mW *1 IC only. In the case of exceeding 25C, 12.0 mW should be reduced at the rating 1C. *2 When packaging a glass epoxy board of 270x70x1.6mm. If exceeding 25C, 17mW should be reduced at the rating 1C. * Has not been designed to withstand radiation. Because this product is specifically designed for a particular device or unit, check in advance if the device or unit is a strategic material stated in the Foreign Exchange law. Be careful of handling this document because contents of this document may fall under the service (technology in the design, the manufacture and the use) defined in the Foreign Exchange and Foreign Trade Control law of Japan. REV.C 2/4 Recommended operating conditions Parameter Symbol Min Typ MaxUnit Parameter Symbol Min Typ Max Unit Power supply voltage 1 Input voltage range ADVDD DAVDD 3.00 3.30 3.60 V VIN1 -0.3 - V (DAC) ADC +0.3 Power supply voltage 2 Input voltage range I1VDD ADVDD 3.00 3.30 3.60 V VIN2 -0.3 - V (ADC) I2C-1 +0.3 Power supply voltage 3 Input voltage range I2VDD I1VDD 2.40 3.30 3.60 V VIN3 -0.3 - V (I2C-1) I2C-2 +0.3 Power supply voltage 4 Input voltage range SDI1 I2VDD 2.40 3.30 3.60 V VIN4 -0.3 - V (I2C-2) SD-CARD VDD+0.3 Power supply voltage 5 Input voltage range CAVDD SDVDD 2.70 3.30 3.60 V VIN5 -0.3 - V (SD-CARD) CAMERA +0.3 Power supply voltage 6 Input voltage range IOVDD CAVDD 2.30 2.85 3.30 V VIN6 -0.3 - V (CAMERA) Other IO +0.3 Power supply voltage 7 Output Current IOVDD 1.70 3.30 3.60 V IOH -13 - - mA (Other IO) *1 Power supply voltage 8 OutputL Current DVDD 1.45 1.50 1.55 V IOL - - 13 mA (Digital CORE) *1 Operating temperature Topr -40 - 85 C range *1 Sum of absolute current of IOs in IOVDD system must be less than 100mA, and every sum of absolute current of IOs in CAVDD, SDVDD, I1VDD and I2VDD system must be less than 26mA. * Please supply power source in order of CORE(DVDD) IOIOVDD,CAVDD,SDVDD,I1VDD,I2VDD,ADVDD,DAVDD * Please keep RESETB terminal is LOW, until power supply is stable. Electric characteristics (Unless otherwise specified, DVDD=1.50V, DAVDD=ADVDD=I1VDD=I2VDD=SDVDD=IOVDD=3.30V, CAVDD=2.85V, DAVSS=ADVSS=DVSS=0.0V, Ta=25C, fXIN=13.5MHz, fAXIN=16.384MHz, fSYS=41.0MHz(Internal Clock with PLL) IOPWR is a generic name of I1VDD,I2VDD,SDVDD,CAVDD,IOVDD.) Specification Parameter Symbol Unit Conditions Min Max Common Input frequency 1 fXIN 5.0 30.0 MHz XIN (Duty 5010%), When PLL is ON. Input frequency 2 fAXIN 8.284 32.768 MHzAXIN(Duty 5010%) Internal clock frequency 1 fSYS - 41.0 MHz When PLL is ON, Except I2S Audio Block Internal clock frequency 2 AUD - 32.768 MHzI2S Audio Block Static consumption current IDDST - 200 A When all clock stop Logic Block Input Leakcurrent IIHL -10 10 AVIH=IOPWR Input Leak current IIHL -10 10 AVIL=V Input Pull down current 1 IIHPD1 25 100 A Pull down pin, VIH=IOVDD Input Pull down current 2 IIHPD2 25 100 A Pull down pin, VIH=CAVDD Input Pull down current IILPD -10 10 A Pull down pin, VIL=V Input H voltage 1 VIH1 IOPWR0.8 IOPWR+0.3 V Normal Input Input L voltage 1 VIL1 -0.3 IOPWR0.2 V Normal Input Input H voltage 2 VIH2 IOPWR0.85 IOPWR+0.3 V Hysteresis input pin Input L voltage 12 VIL2 -0.3 IOPWR0.15 V (TIM TRIG,NTRST,RESETB,BIT SEL,TCM SEL,AUTO READ) Output H voltage 1 VOH1 IOPWR-0.4 IOPWR V IOH=-2.0mA(DC), Output except SD CLK, When CAVDD=3.3V Output L voltage 1 VOL1 0.0 0.4 V IOL=2.0mA(DC), Output except SD CLK, When CAVDD=3.3V. Output H voltage 2 VOH2 IOPWR-0.4 IOPWR V IOH=-4.0mA(DC)SD CLK Output L voltage 2 VOL2 0.0 0.4 V IOL=4.0mA(DC)SD CLK DACBlock DAC Bit Width RES DA - 10 bits DAC Operating current IDDDA 32 42 mA R =37.5R =2.4kDAVDD Pin current L IREF DAC Static consumption current IDDSTDA - 5 uA R =37.5R =2.4kDAVDD Pin current L IREF Integral Non-linearity INL DA -8.0 +8.0 LSB R =37.5R =2.4k L IREF Differential Non-linearity DNL DA -2.0 +2.0 LSB R =37.5R =2.4k L IREF Full scale voltage VFS DA 1.1 1.4 V R =37.5R =2.4k L IREF ADCBlock ADC Bit Width RES AD - 8 bits Input voltage range(Upper Limit) VIN AD T ADVDD0.85 ADVDD0.95 V Input voltage range(Lower Limit) VIN AD B ADVDD0.05 ADVDD0.15 V Integral Non-linearity INL AD -2.0 +2.0 LSB Differential Non-linearity DNL AD -2.0 +2.0 LSB Change Standard clock cycle ADC 4.0 16.0 MHz Sample per second Change cycle fsps 30.8K 123K sps Need 130*ADC CLK for conversion by sweeping REV. C