For Home Electronics and Security Devices Camera Image Processor Series Camera Image Processor Compatible with MPEG4 Video BU6582GVW No.09061EBT03 Description BU6582GVW is a camera image processor compatible with MPEG4 movies. MPEG4 compatibility enables seamless video transmission with other devices. Features 1) Built-in Camera Module Interface SXGA size (12801024) for input of image data up to 15 fps and VGA size (640480) for input of image data up to 30fps (zooming function available). Input data format for YUV=4:2:2, RGB=4:4:4. Filter processing (image processing) to input images (2 gradations / gray scale / sepia / emboss / edge enhancement/ negative). Multi-step size reduction down to 1/16 in X- and Y-direction possible. Cutting out into an arbitrary size after resizing. D range enlargement processing of Y (brightness) available in YUV color space to cut images. Cut images to be stored into an arbitrary position in frame memory in YUV=4:2:2 or RGB=5:6:5 format. 2-line serial interface built in for camera module control. Image processing of data written by HOST CPU in YUV or RGB format possible through camera module interface. 2) Built-in frame memory / JPEG code memory Image frame memory built in (160KB to store 1 frame of 320 240 16bit/pixel during normal mode or 50KB/frame to store 2 frames of 176 144 16bit/pixel during MPEG4/H.263 mode). Display area settable to an arbitrary LCD size. Data to be stored into image frame memory in YUV=4:2:2 or RGB5:6:5 (16bit/pixel) format. Mask data to be stored into mask frame memory in 1bit/2pixels in YUV=4:2:2 or 1bit/1pixels in RGB=5:6:5 format. An arbitrary position of frame memory to be updated to camera image according to mask memory. Image frame memory accessible from host CPU (access available both in RGB and YUV). Rectangular writing function and rectangular reading function for transparent color to image frame memory. Frame memory usable as JPEG code memory (160KB) to store JPEG compressed images. Frame memory usable as a ring buffer for JPEG code of 160KB or more. 3) Built-in LCD controller interface Built-in input/output interface to LCD controller For display colors of 262144 colors / 65536 colors / 4096 colors. Up to 2 LCD module controllers controllable. Arbitrary rectangular selection in frame memory to be transferred to LCD controller. Multi-step scaling process in the range of 1/4 to 2 in X- and Y-direction is available to display images from the frame memory to the LCD. www.rohm.com 2009.04 - Rev.B 1/16 2009 ROHM Co., Ltd. All rights reserved. Technical Note BU6582GVW 4)Built-in MPEG4 Codec ISO/IEC14496 conforming simple profile level 0. ISO/IEC 14496 conforming simple profile level 1 (4 objects can be supported in decode mode). ITU-T H.263 conforming profile 0 level 10. ITU-T H.263 conforming profile 3 level 10. MAX QCIF (176x144), SQCIF (128x96), 96x80. For input image data up to 15fps. 5)Built-in JPEG CODEC ISO/IEC10918 conforming base line method. Compression For YUV=4:2:2 only. Quantization table selectable from 20 built-in tables. Decompression For YUV=4:4:4, 4:2:2(horizontal sub-sampling), 4:2:0, 4:1:1(horizontal sub-sampling), and gray scale. 6) Built-in HOST CPU interface Adaptable to 16bit bus interface. Read/ write access to frame memory. Read/ write access to internal registers (Indirect access with a index register as the address). Read/ write access to the LCD controller: Parallel/Serial (Direct access available via the LCD interface). 7) Extended overlay function Supporting overlay of icon-data/font-data of up to two points during LCD data transfer. Both icon-data and font-data corresponding to 65536 display colors. Possible to setting transparent colors. 8) LED interface, GIO function Built-in PWM output of 4 systems for 3 color LED controls and white LED control. A total of 19 pins available for the GIO function (7 out of the 19 pins can be shared for other functions.) 9) Clock generation, power management function Oscillation circuit configuration by XIN and XOUT terminals, or clock input from XIN terminal available. Built-in PLL. Clock control of IC inside in unit of block (suspend mode available). 10) Key interfaces built in 3 systems of key interfaces built in. Interruption to be generated at key input. Useable for removing software chattering. Data is prepared separately about each register setup. Please refer to the Development Scheme on page 14. System 1 (VDDIO1) System 2 (VDDIO2) P3-P10(D15-8), P13-P14(SGIO3-2), P37(INT), P39-P43(SGIO11-10, CAMVS, CAMHS, CAMD0), P46-P47(CAMD1-2), P49-P53(SGIO9, P17(SGIO1), P19(D7), CAMD3, GIO2/KEY2, CAMD4, CAMD5), P55-P56(CAMD6, CAMD7), P58-P59(CAMCKI-CAMCKO), P21-29(D6-5,SGIO0,D4-0,A2), P63-P68(SDA, SDC, LEDCNT/GIO1, PWM1/GIO3, PWM2/GIO4, PWM3/GIO5), P33-P36(A1,CSB,WRB,RDB), P70-P75(VD/GIO6, LCDCS1B, LCDCS2B, KEY0, LCDD16, SGIO8), P77-P79(LCDWRB, SGIO7, P118-P119(XOUT,XIN) LCDRDB), P81-P82(LCDA0, SGIO4), P84-P88(LCDD0-4), P92-98(LCDD5, LCDD6/SCL, SGIO6, LCDD7/SI, SGIO5, TEST, LCSS17), P100(LCDD8), P103-105(LCDD9-11), P107-109(LCDD12, KEY1, LCDD13), P111-P114(LCDD14-15, RESETB, PWM0/GIO0) Application Security camera, Intercom with camera, Drive recorder, and Web camera etc. Lineup Power source voltage Camera HOST CPU LCD Multimedia Parameter Codec Image Package IO1:HOST CPU I/F interface interface interface interface IO2:Camera, LCD MPEG4/H.263 Codec 1.45-1.55V(V Core) Supported up to 16bit bus Supported up DD 1.3M pixels JPEG - BU6582GVW 1.7-3.15V(V IO1) 1.3M pixels. 80 systems to QVGA SBGA120W080 DD Codec 2.55-3.15V(V IO2) (12801024) CPU Interface (320240) DD Motion-JPEG www.rohm.com 2009.04 - Rev.B 2/16 2009 ROHM Co., Ltd. All rights reserved.