BU90R102-Z ROHM

Datasheet LVDS Interface LSI 67bit LVDS Receiver BU90R102 General Description Key Specifications 2.30 to 3.60 V The BU90R102 receiver operates from 8MHz to 160MHz Supply Voltage Range 8 to 160 MHz wide clock range. Operating Frequency The BU90R102 converts the 10 Lane (2Channel) LVDS Operating Temperature Range -40 to +85 serial data streams back into 67bit of LVCMOS parallel data. Package W(Typ) x D(Typ) x H(Max) Data is transmitted seven times (7X) stream and reduce HQFP144VM 20.0mm 20.0mm 1.6mm the cable number by 3(1/3) or less. I/O Voltage range is 2.3 to 3.6V, so it is available for many products. Applications Flexible Input /Output mode is suitable for a variety of Security camera, Digital camera application Interface. Tablet Flat panel display Features Power down mode The maximum data rate is 1120Mbps/Lane Clock edge selectable It enables to receive the 60bit of RGB data, Support spread spectrum clock generator input 7bit of Timing and Control data Support clock frequency from 8MHz up to 160MHz Flexible Input /Output mode 1. Single-in / Single-out 2. Single-in / Dual-out 3. Dual-in / Single-out 4. Dual-in / Dual-out Block Diagram Figure 1. Block Diagram Product structure : Silicon monolithic integrated circuit This product has no designed protection against radioactive rays . www.rohm.com TSZ02201-0L2L0H500280-1-2 2014 ROHM Co., Ltd. All rights reserved. 1/26 TSZ22111 14 001 02.Oct.2014 Rev.001Datasheet BU90R102 Contents General Description .................................................................................................................................................... 1 Key Specifications ...................................................................................................................................................... 1 Package ....................................................................................................................................................................... 1 Applications ................................................................................................................................................................ 1 Features ..................................................................................................................................................................... 1 Block Diagram ............................................................................................................................................................. 1 Figure 1. Block Diagram ......................................................................................................................................... 1 Pin Configuration ........................................................................................................................................................ 3 Figure 2. Pin Configuration .................................................................................................................................... 3 Pin Descriptions ......................................................................................................................................................... 4 Absolute Maximum Ratings ..................................................................................................................................... 6 Recommended Operating Conditions ...................................................................................................................... 6 Figure 3. Differential input CLK ............................................................................................................................. 6 DC Characteristic ........................................................................................................................................................ 7 Figure 4. LVDS Receiver DC Specifications ......................................................................................................... 7 AC Characteristic ........................................................................................................................................................ 8 Supply Current ............................................................................................................................................................ 9 Figure 5. Test Pattern ............................................................................................................................................ 9 AC Timing Diagrams................................................................................................................................................. 10 Figure 6. LVCMOS Output Load and Transition Time ...................................................................................... 10 Figure 7. CLKOUT Period and High/Low Time ................................................................................................. 10 Figure 8. CLKOUT Position and Setup/Hold Timing ........................................................................................ 10 Figure 9. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode .................................. 11 Figure 10. LVDS Input Data Position ................................................................................................................. 11 Figure 11. Phase Locked Loop Set Time .......................................................................................................... 12 Figure 12. RCLK+/- to CLKOUT Delay ............................................................................................................... 12 Figure 13. RC1 (DE) Input Timing (Single-in / Dual-out mode) ....................................................................... 13 Output Data Mapping ................................................................................................................................................ 14 LVDS Input Data Mapping ........................................................................................................................................ 16 Figure 14. LVDS Input Data Mapping MODE1=H (Single-in Mode) ................................................................. 16 Figure 15. LVDS Input Data Mapping MODE1=L (Dual-in Mode) .................................................................... 16 Typical Application Circuit ....................................................................................................................................... 21 Figure 16. Typical Application Circuit (24bit Dual-in/Dual-out mode) ............................................................ 21 Operational Notes ..................................................................................................................................................... 22 Ordering Information ................................................................................................................................................ 24 Marking Diagram ....................................................................................................................................................... 24 Physical Dimension, Tray Information ................................................................................................................... 25 Revision History ....................................................................................................................................................... 26 www.rohm.com TSZ02201-0L2L0H500280-1-2 2014 ROHM Co., Ltd. All rights reserved. 2/26 TSZ22111 15 001 02.Oct.2014 Rev.001