FEDL610Q772-01 Issue Date: Dec. 11, 2015 ML610Q772 8-bit Microcontroller GENERAL DESCRIPTION 2 This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART, I C bus interface (master/slave), synchronous serial port, voltage level supervisor analog comparators and 10-bit successive approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel processing. The Flash ROM that is installed as program memory, and the on-chip debug function that is installed, enable program debugging and programming on customers board. FEATURES CPU 8-bit RISC CPU (CPU name: nX-U8/100) Instruction system: 16-bit instructions Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on On-Chip debug function Minimum instruction execution time: 30.5us ( 32.768kHz system clock) 0.122us ( 8.192MHz system clock) Internal memory Flash memory: Internal 32Kbyte Flash memory (16K x 16bit) for program including unusable 32byte test data area. Internal 4Kbyte Flash memory (2K x 16bit) for data. SRAM memory: Internal 4Kbyte data RAM (4K x 8bit) Flash Memory operating condition and specification Refer to the chapter Electrical characteristics FLASH MEMORY SPECIFIACTION. Interrupt controller 1 non-maskable interrupt source (Internal source: 1(WDT)) 30 maskable interrupt sources (Internal sources: 23, External source: 7) Time base counter (TBC) Low-speed time base counter: 1 channel High-speed time base counter: 1 channel (This time base counter is divided by 1-16, and then it can be used as a clock of the Timer and PWM.) 1/24 FEDL610Q772-01 ML610Q772 Watchdog timer (WDT) Non-maskable interrupt and reset (Non-maskable interrupt is generated by the first overflow, and reset is generated by the second overflow) Free running Overflow period: 7 types selectable by software (23.4ms, 31.25ms, 62.5ms, 125ms, 500ms, 2s, and 8s) Timer 8-bit x 6 channels (16-bit configuration available, 16-bit x 3ch) Supports auto reload timer mode/One shot timer mode Timer count start/stop by software or external input trigger (Timer function with external trigger input supports for only 2ch. Selectable external pins/analog comparator output as an exeternal trigger.) The effective minimum pulse width of the external trigger input: Timer clock 3 (about 183 ns 16.384 MHz) Allows measurement of pulse width etc. using an external trigger input. 8-selectable clock frequency as counter clock per channel PWM Resolution 16-bit Single output x 3ch, Multiple three outputs x 1ch Allows an output of the PWM signal in a cycle of about 122ns ( PLLCLK = 16.384MHz) to 2s ( LSCLK = 32.768kHz) Supports one shot PWM mode PWM start/stop by software and external trigger input (Selectable external pins, analog comparator output or timer interrupt as external trigger) 3-selectable clock frequency as PWM clock per channel UART TXD/RXD x 2ch Half-Duplex Communication Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits Positive logic/negative logic selectable Built-in baud rate generator 2 I C bus interface Master function: standard mode (100kbit/s 8MHz), Fast mode (400kbit/s 8MHz) Slave function : standard mode (100kbit/s) Synchronous serial port (SSIO) 1ch Master/slave selectable LSB first/MSB first selectable 8-bit length/16-bit length selectable Successive approximation type A/D converter (SA-ADC) 10-bit A/D converter 8ch Analog Input 2/24