GN4124 x4 Lane PCI Express to Local Bridge Data Sheet GN4124 x4 Lane PCI Express to Local Bridge www.gennum.com 1 of 31 Data Sheet 48407 - 1 May 2009 Proprietary & ConfidentialRevision History Version ECR Date Changes and Modifications 2 151915 May 2009 Created new document describing functionality and the register map for GN4124 & GN4121 devices. These common sections have been removed. 1 151527 May 2009 It is now a Data Sheet. Added the content of the document: GN4124 x4 PCI Express to Local Bus Bridge User Manual (Document ID: 47719) to this data sheet. This User Manual is no longer a stand-alone document. Changed some parameters in Table 2-1 (EEPROM EN), Table 3-2, Table 3-3, Table 5-2 and Table 13-2. Changed Figure 4-2, Figure 6-2, Figure 7-1 and Figure 9-16. Modified descriptions in 9.4 Operation, 9.7.3 FCL FPGA Configuration and 9.7.4 FCL FSM FPGA Configuration. Changes to registers to PCI BAR0 LOW, PCI BAR2 LOW, PCI BAR2 HIGH, PCI BAR4 LOW, PCI BAR4 HIGH, PCI SUB VENDOR, PCI SUB SYS, PCIE DEVICE CAP, PCIE DCR, INT CTRL, INT STAT, INT CFG0-7, GPIO DIRECTION MODE, GPIO OUTPUT ENABLE, GPIO OUTPUT VALUE, GPIO INT MASK, GPIO INT MASK CLR (Note: formerly GPIO INT ENABLE), GPIO INT MASK SET (Note: formerly GPIO INT DISABLE), GPIO INT STATUS, GPIO INT TYPE, GPIO INT VALUE, GPIO INT ON ANY and FCL CTRL. D 151519 March 2009 Clarified output voltage and local bus timing in Table 3-6 and Table 3-11. C 150789 December 2008 Corrected pin assignments and definitions. Updated electrical characteristics. Corrected Figure 2-2. Updated Local Bus Interface clock range. B 150182 August 2008 Corrected pin assignments, part number and other updates. A 148626 May 2008 New document. Contents 1. Introduction.....................................................................................................................................................4 1.1 Features ...............................................................................................................................................4 1.2 Live on Power-up ..............................................................................................................................5 1.3 FPGA On-the-Fly Configuration Loader ...................................................................................6 1.4 Local Bus Interface ...........................................................................................................................6 1.5 Virtual Channel Support ................................................................................................................6 1.6 PCI Express Application Layer ....................................................................................................7 1.7 Interrupt Controller .........................................................................................................................7 1.8 2-Wire Serial Controller .................................................................................................................7 1.9 Data Sheet Usage ..............................................................................................................................7 1.10 Getting Help from Gennum ........................................................................................................8 GN4124 x4 Lane PCI Express to Local Bridge 2 of 31 Data Sheet 48407 - 1 May 2009 Proprietary & Confidential