GS1535 HD-LINX II Multi-Rate SDI Automatic Reclocker GS1535 Data Sheet Key Features Description SMPTE 292M, 259M and 344M compliant The GS1535 Multi-Rate Serial Digital Reclocker is designed to automatically recover the embedded clock Supports data rates of 143, 177, 270, 360, 540, signal and re-time the data from a SMPTE 292M, 1483.5, 1485 Mb/s SMPTE 259M or SMPTE 344M compliant digital video Supports DVB-ASI at 270Mb/s signal. Auto and Manual Modes for rate selection The device removes the high frequency jitter Standards indication in Auto Mode components from the bit-serial stream. Input 4:1 input multiplexor termination is on-chip for seamless matching to 50 Lock Detect Output transmission lines. An LVPECL compliant output interfaces seamlessly to the GS1528 Cable Driver On-chip Input and Output Termination Differential inputs and outputs The GS1535 can operate in either auto or manual rate selection mode. In Auto mode the GS1535 Configuarble automatic Mute or Bypass when not automatically detects and locks onto an incoming locked SMPTE SDI data signal from 143 Mb/s to 1.485 Gb/s. Manual Bypass function For single rate data systems, the GS1535 can be SD/HD indication output to control GS1528 Dual configured to operate in manual mode. In both modes, Slew-Rate Cable Driver the GS1535 requires only one external crystal to set the Pb-free and Green VCO frequency when not locked and provides adjustment free operation. In systems which require Single 3.3V power supply passing non-SMPTE data rates, the GS1535 will Operating temperature range: 0C to 70C automatically or manually enter a bypass mode in order to pass the signal without reclocking. Applications SMPTE 292M, SMPTE 259M and SMPTE 344M The ASI/177 input pin allows for manual selection of Serial Digital Interfaces support of either 177Mb/s or DVB-ASI inputs. XTAL XTAL XTAL+ XTAL- OUT+ OUT- LF+LF- KBB XTAL BUFFER RE-TIMER OSC M DATA BUFFER DDO/DDO U X DDO MUTE DDI 0 PHASE FREQUENCY CHARGE M VCO DETECTOR PUMP U D X A DDI 1 T A PHASE DETECTOR M DDI 2 U DIVIDE BY X 2,4,6,8,12,16 DIVIDE BY DDI 3 152, 160, 208 BYPASS CONTROL LOGIC LOGIC DDI SEL 1:0 SS 2:0 ASI/177 LD AUTO/MAN AUTOBYPASS BYPASS GS1535 Functional Block Diagram 18557 - 8 February 2005 1 of 22 www.gennum.comGS1535 Data Sheet Contents Key Features.................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................3 1.1 Pin Assignment ...............................................................................................3 1.2 Pin Descriptions ..............................................................................................4 2. Electrical Characteristics...........................................................................................7 2.1 Absolute Maximum Ratings ............................................................................7 2.2 DC Electrical Characteristics ..........................................................................7 2.3 AC Electrical Characteristics ...........................................................................8 2.4 Input/Output Circuits .....................................................................................10 3. Detailed Description ................................................................................................13 3.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................13 3.2 VCO ..............................................................................................................14 3.3 Charge Pump ................................................................................................14 3.4 Frequency Acquisition Loop The Phase-Frequency Detector ...................14 3.5 Phase Acquisition Loop The Phase Detector ...........................................15 3.6 4:1 Input Mux ................................................................................................15 3.7 Automatic And Manual Data Rate Selection .................................................16 3.8 Bypass Mode ................................................................................................17 3.9 DVB/ASI Operation .......................................................................................17 3.10 LOCK ..........................................................................................................17 3.11 Output Drivers .............................................................................................18 3.12 Output Mute ................................................................................................18 4. Application Reference Design.................................................................................19 4.1 Typical Application Circuit .............................................................................19 5. References..............................................................................................................20 6. Package & Ordering Information.............................................................................20 6.1 Package Dimensions ....................................................................................20 6.2 Packaging Data .............................................................................................21 6.3 Ordering Information .....................................................................................21 7. Revision History ......................................................................................................22 18557 - 8 February 2005 2 of 22