GS2960A 3Gb/s, HD, SD SDI Receiver Complete with SMPTE Video Processing Key Features Application: Dual Link (HD-SDI) Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s, to Single Link (3G-SDI) Converter 1.485/1.001Gb/s and 270Mb/s HD-SDI 10-bit Link A HD-SDI 10-bit Deserializer FIFO Supports SMPTE 425M (Level A and Level B), SMPTE GS2960A HVF/PCLK 3G-SDI WR 424M, SMPTE 292, SMPTE 259M-C and DVB-ASI HVF/PCLK GS2962 HD-SDI 10-bit Link B HD-SDI 10-bit Integrated Reclocker Deserializer FIFO HVF/PCLK GS2960A WR Integrated low phase noise VCO Serial digital reclocked, or non-reclocked loop-through GS4910 HVF output Ancillary data extraction XTAL Optional conversion from SMPTE 425M Level B to Description Level A for 1080p 50/60 4:2:2 10-bit inputs The GS2960A is a multi-rate SDI Receiver which includes Parallel data bus selectable as either 20-bit or 10-bit complete SMPTE processing, as per SMPTE 425M, 292 and Comprehensive error detection and correction SMPTE 259M-C. The SMPTE processing features can be features bypassed to support signals with other coding schemes. Output H, V, F or CEA 861 Timing Signals The device features an integrated Reclocker with an 1.2V digital core power supply, 1.2V and 3.3V analog internal VCO and a wide Input Jitter Tolerance (IJT) of power supplies, and selectable 1.8V or 3.3V I/O power 0.7UI. supply A serial digital loop through output is provided, which can GSPI Host Interface be configured to output either reclocked or non-reclocked Wide temperature range of -40C to +85C serial digital data. The Serial Digital Output can be Low power operation (typically 350 mW) connected to an external Cable Driver. Small 11mm x 11mm 100-ball BGA package The device operates in one of four basic modes: SMPTE Pb-free and RoHS compliant mode, DVB-ASI mode, Data-Through mode or Standby mode. In SMPTE mode, the GS2960A performs SMPTE Applications de-scrambling and NRZI to NRZ decoding and word alignment. Line-based CRC errors, line number errors, TRS Application: Single Link (3G-SDI) errors and ancillary data check sum errors can all be to Dual Link (HD-SDI) Converter detected. The GS2960A also provides ancillary data 10-bit HD-SDI extraction. The entire ancillary data packet is extracted, GS2962 Link A HVF/PCLK and written to host-accessible registers. Other processing Gennum 3G-SDI GS2960A Equalizer functions include H:V:F timing extraction, Luma and HVF/PCLK 10-bit HD-SDI Chroma ancillary data indication, video standard GS2962 Link B detection, and SMPTE 352M packet detection and decoding. All of the processing features are optional and may be enabled or disabled via the Host Interface. GS2960A 3Gb/s, HD, SD SDI Receiver 1 of 99 www.semtech.com Data Sheet 54384 - 2 September 2012 LOCKED H/HSync V/VSync F/De Rate Det 1:0 Error Flags YANC/CANC Both SMPTE 425M Level A and Level B inputs are 20-bit parallel bus as Y on 10 bits and Cb/Cr on the other 10 supported. The GS2960A also provides user-selectable bits. As such, this parallel bus can interface directly with conversion from Level B to Level A for 1080p 50/60 4:2:2 video processor ICs. For other SMPTE 425M mapping 10-bit formats only. structures, the video data is mapped to a 20-bit virtual interface as described in SMPTE 425M. In all cases this In DVB-ASI mode, sync word detection, alignment and 20-bit parallel bus can be multiplexed onto 10 bits for a low 8b/10b decoding is applied to the received data stream. pin count interface with downstream devices. The In Data-Through mode all forms of SMPTE and DVB-ASI associated Parallel Clock input signal operates at 148.5 or processing are disabled, and the device can be used as a 148.5/1.001MHz (for all 3Gb/s HD 10-bit multiplexed simple serial to parallel converter. modes), 74.25 or 74.25/1.001MHz (for HD 20-bit mode), 27MHz (for SD 10-bit mode) and 13.5MHz (for SD 20-bit The device can also be placed in a lower power Standby mode). mode. In this mode, no signal processing is carried out and the parallel output is held static. Note: for 3Gb/s 10-bit mode the device operates in Dual Data Rate (DDR) mode, where the data is sampled at both Parallel data outputs are provided in 20-bit or 10-bit the rising and falling edges of the clock. This reduces the I/O multiplexed format for 3Gb/s, HD and SD video rates. For speed requirements of the downstream devices. 1080p 50/60 4:2:2 10-bit, the parallel data is output on the Functional Block Diagram Crystal Host GSPI and Buffer/ JTAG Controller Interface Oscillator VBG LB CONT LF PCLK Illegal code remap, Output Mux/ Flywheel TRS ANC/ TRS/ SDI Reclocker Serial Mux DOUT 19:0 Descramble, SMPTE 425M Line Number/ Demux Video Detect Checksum with to Word Align, Level B Level A TERM Buffer Standard Timing /352M CRS Integrated Parallel Rate Detect 1080p 50/60 4:2:2 10-bit Insertion, Detect Extraction Extraction SDI VCO Converter EDH Packet Insertion DVB-ASI Decoder SDO Buffer Mux SDO I/O Control STAT 5:0 GS2960A Functional Block Diagram GS2960A 3Gb/s, HD, SD SDI Receiver 2 of 99 Data Sheet 54384 - 2 September 2012 SDO EN/DIS VCO VDD VCO GND PLL VDD RC BYP PLL GND BUFF VDD BUFF GND XTAL1 EQ VDD XTAL2 EQ GND XTAL OUT A VDD A GND JTAG/HOST SDIN TDI SCLK TCLK CS TMS SDOUT TDO RESET TRST STANDBY IOPROC EN/DIS SMPTE BYPASS 20BIT/10BIT TIM861 SW EN DVB ASI CORE VDD CORE GND IO VDD IO GND