SX1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET SX1231H Transceiver Low Power Integrated UHF Transceiver with On-Chip +20dBm PA VBAT1&2 VR ANA VR DIG RC Power Distribution System Oscillator / LNA Mixers Modulators Single to Differential RFIO RESET SPI RXTX RSSI AFC GND Division by 2, 4 or 6 DIO0 Tank PA0 DIO1 Inductor DIO2 Ramp & Loop Frac-N PLL VR PA Filter DIO3 Control Synthesizer DIO4 DIO5 XO PA BOOST 32 MHz PA1&2 XTAL GND GENERAL DESCRIPTION KEY PRODUCT FEATURES The SX1231H is a highly integrated RF transceiver capable +20 dBm - 100 mW Power Output Capability of operation over a wide frequency range, including the 433, 868 and 915 MHz license-free ISM (Industry Scientific and High Sensitivity: down to -120 dBm at 1.2 kbps Medical) frequency bands. Its highly integrated architecture High Selectivity: 16-tap FIR Channel Filter allows for a minimum of external components whilst maintaining maximum design flexibility. All major RF Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image Frequency response communication parameters are programmable and most of them can be dynamically set. The SX1231H offers the Low current: Rx = 16 mA, 100nA register retention unique advantage of programmable narrow-band and wide- Programmable Pout: -18 to +20 dBm in 1dB steps band communication modes without the need to modify external components. The SX1231H is optimized for low Constant RF performance over voltage range of chip power consumption while offering high RF output power and FSK Bit rates up to 300 kb/s channelized operation. TrueRF technology enables a low- Fully integrated synthesizer with a resolution of 61 Hz cost external component count (elimination of the SAW filter) whilst still satisfying ETSI and FCC regulations. FSK, GFSK, MSK, GMSK and OOK modulations Built-in Bit Synchronizer performing Clock Recovery APPLICATIONS Incoming Sync Word Recognition Automated Meter Reading 115 dB+ Dynamic Range RSSI Wireless Sensor Networks Automatic RF Sense with ultra-fast AFC Home and Building Automation Packet engine with CRC-16, AES-128, 66-byte FIFO Wireless Alarm and Security Systems Built-in temperature sensor Industrial Monitoring and Control ORDERING INFORMATION Wireless M-BUS Part Number Delivery MOQ / Multiple MARKETS SX1231HIMLTRT Tape & Reel 3000 pieces Europe: EN 300-220-1 QFN 24 Package - Operating Range -40 +85C North America: FCC Part 15.247, 15.249, 15.231 Pb-free, Halogen free, RoHS/WEEE compliant product Rev 1 - Oct 2011 Page 1 www.semtech.com Interpolation Decimation and & Filtering & Filtering Demodulator & Modulator Bit Synchronizer Packet Engine & 66 Bytes FIFO Control Registers - Shift Registers - SPI InterfaceSX1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET Table of Contents Page 1. General Description................................................................................................................................................ 8 1.1. Simplified Block Diagram ................................................................................................................................ 8 1.2. Pin and Marking Diagram................................................................................................................................ 9 1.3. Pin Description.............................................................................................................................................. 10 2. Electrical Characteristics....................................................................................................................................... 11 2.1. ESD Notice.................................................................................................................................................... 11 2.2. Absolute Maximum Ratings .......................................................................................................................... 11 2.3. Operating Range........................................................................................................................................... 11 2.4. Chip Specification......................................................................................................................................... 12 2.4.1. Power Consumption ................................................................................................................................. 12 2.4.2. Frequency Synthesis................................................................................................................................ 12 2.4.3. Receiver ................................................................................................................................................... 13 2.4.4. Transmitter ............................................................................................................................................... 14 2.4.5. Digital Specification ...................................................................................................................................15 3. Chip Description.................................................................................................................................................... 16 3.1. Power Supply Strategy.................................................................................................................................. 16 3.2. Frequency Synthesis..................................................................................................................................... 16 3.2.1. Reference Oscillator................................................................................................................................. 16 3.2.2. CLKOUT Output ........................................................................................................................................17 3.2.3. PLL Architecture....................................................................................................................................... 17 3.2.4. Lock Time.................................................................................................................................................. 18 3.2.5. Lock Detect Indicator................................................................................................................................ 18 3.3. Transmitter Description ................................................................................................................................. 19 3.3.1. Architecture Description ........................................................................................................................... 19 3.3.2. Bit Rate Setting ........................................................................................................................................ 19 3.3.3. FSK Modulation........................................................................................................................................ 20 3.3.4. OOK Modulation....................................................................................................................................... 20 3.3.5. Modulation Shaping.................................................................................................................................. 21 3.3.6. Power Amplifiers ...................................................................................................................................... 21 3.3.7. High Power Settings ..................................................................................................................................22 3.3.8. Output Power Summary ........................................................................................................................... 22 3.3.9. Over Current Protection ........................................................................................................................... 22 3.4. Receiver Description..................................................................................................................................... 23 3.4.1. Block Diagram .......................................................................................................................................... 23 3.4.2. LNA - Single to Differential Buffer ............................................................................................................ 23 3.4.3. Automatic Gain Control ............................................................................................................................ 24 3.4.4. Continuous-Time DAGC........................................................................................................................... 25 3.4.5. Quadrature Mixer - ADCs - Decimators.................................................................................................... 26 3.4.6. Channel Filter ........................................................................................................................................... 26 3.4.7. DC Cancellation ....................................................................................................................................... 27 Rev 1 - Oct 2011 Page 2 www.semtech.com