SX1233IMLTRT Semtech

SX1233 WIRELESS & SENSING DATASHEET SX1233 High Bit Rate Transceiver Low Power Integrated UHF Transceiver VBAT1&2 VR ANA VR DIG RC Power Distribution System Oscillator / LNA Mixers Modulators Single to Differential RFIO RESET SPI RXTX RSSI AFC GND Division by 2, 4 or 6 DIO0 Tank PA0 DIO1 Inductor DIO2 Ramp & Loop Frac-N PLL VR PA Filter DIO3 Control Synthesizer DIO4 DIO5 XO PA BOOST 32 MHz PA1&2 XTAL GND GENERAL DESCRIPTION KEY PRODUCT FEATURES The SX1233 is a highly integrated RF transceiver capable of Programmable bit rate up to 600kbps (FSK) operation over a wide frequency range, including the 433, High Sensitivity: down to -120 dBm at 1.2 kbps 868 and 915 MHz license-free ISM (Industry Scientific and Medical) frequency bands. Its highly integrated architecture High Selectivity: 16-tap FIR Channel Filter allows for a minimum of external components whilst Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, maintaining maximum design flexibility. All major RF 80 dB Blocking Immunity, no Image Frequency response communication parameters are programmable and most of Low current: Rx = 16 mA, 100nA register retention them can be dynamically set. The SX1233 offers the unique advantage of programmable narrow-band and wide-band Programmable Pout: -18 to +17 dBm in 1dB steps communication modes without the need to modify external Constant RF performance over voltage range of chip components. The SX1233 is optimized for low power Fully integrated synthesizer with a resolution of 61 Hz consumption while offering high RF output power and channelized operation. TrueRF technology enables a low- FSK, GFSK, MSK, GMSK and OOK modulations cost external component count (elimination of the SAW Built-in Bit Synchronizer performing Clock Recovery filter) whilst still satisfying ETSI and FCC regulations. SX1233 is pin to pin compatible with SX1231 and SX1239. Incoming Sync Word Recognition 115 dB+ Dynamic Range RSSI APPLICATIONS Automatic RF Sense with ultra-fast AFC Automated Meter Reading Packet engine with CRC, AES-128 encryption and 66- byte FIFO Wireless Sensor Networks Built-in temperature sensor and Low Battery indicator Home and Building Automation Wireless Alarm and Security Systems ORDERING INFORMATION Industrial Monitoring and Control Part Number Delivery MOQ / Multiple MARKETS SX1233IMLTRT Tape & Reel 3000 pieces Europe: EN 300-220-1 North America: FCC Part 15.247, 15.249, 15.231 QFN 24 Package - Operating Range -40 +85C Narrow Korean and Japanese bands, Arib STD T-108 Pb-free, Halogen free, RoHS/WEEE compliant product Rev. 7 - July 2013 Page 1 www.semtech.com 2013 Semtech Corporation Interpolation Decimation and & Filtering & Filtering Demodulator & Modulator Bit Synchronizer Packet Engine & 66 Bytes FIFO Control Registers - Shift Registers - SPI InterfaceSX1233 WIRELESS & SENSING DATASHEET Table of contents Section Page 1. General Description ................................................................................................................................................. 8 1.1. Simplified Block Diagram ................................................................................................................................. 8 1.2. Pin and Marking Diagram ................................................................................................................................9 1.3. Pin Description ...............................................................................................................................................10 2. Electrical Characteristics ....................................................................................................................................... 11 2.1. ESD Notice .................................................................................................................................................... 11 2.2. Absolute Maximum Ratings ........................................................................................................................... 11 2.3. Operating Range............................................................................................................................................ 11 2.4. Chip Specification ..........................................................................................................................................12 2.4.1. Power Consumption.................................................................................................................................. 12 2.4.2. Frequency Synthesis................................................................................................................................. 12 2.4.3. Receiver .................................................................................................................................................... 13 2.4.4. Transmitter ................................................................................................................................................ 14 2.4.5. Digital Specification ...................................................................................................................................15 3. Chip Description .................................................................................................................................................... 16 3.1. Power Supply Strategy .................................................................................................................................. 16 3.2. Low Battery Detector ..................................................................................................................................... 16 3.3. Frequency Synthesis ..................................................................................................................................... 16 3.3.1. Reference Oscillator.................................................................................................................................. 16 3.3.2. CLKOUT Output ........................................................................................................................................17 3.3.3. PLL Architecture........................................................................................................................................ 17 3.3.4. Lock Time ..................................................................................................................................................18 3.3.5. Lock Detect Indicator................................................................................................................................. 18 3.4. Transmitter Description ..................................................................................................................................19 3.4.1. Architecture Description ............................................................................................................................ 19 3.4.2. Bit Rate Setting ......................................................................................................................................... 19 3.4.3. FSK Modulation......................................................................................................................................... 20 3.4.4. OOK Modulation........................................................................................................................................ 21 3.4.5. Modulation Shaping................................................................................................................................... 21 3.4.6. Power Amplifiers ....................................................................................................................................... 21 3.4.7. Over Current Protection ............................................................................................................................ 22 3.5. Receiver Description ......................................................................................................................................23 3.5.1. Block Diagram........................................................................................................................................... 23 3.5.2. LNA - Single to Differential Buffer ............................................................................................................. 23 3.5.3. Automatic Gain Control ............................................................................................................................. 24 3.5.4. Continuous-Time DAGC............................................................................................................................ 25 3.5.5. Quadrature Mixer - ADCs - Decimators ....................................................................................................26 3.5.6. Channel Filter............................................................................................................................................ 26 3.5.7. DC Cancellation ........................................................................................................................................ 27 Rev. 7 - July 2013 Page 2 www.semtech.com 2013 Semtech Corporation