SLG46534V-SKT Silego

SLG46534 GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine Features Pin Configuration Logic & Mixed Signal Circuits Highly Versatile Macrocells Read Back Protection (Read Lock) 1.8 V (5%) to 5 V (10%) Supply 1 12 Operating Temperature Range: -40C to 85C VDD GPIO RoHS Compliant / Halogen-Free 14 13 2 11 GPI GPIO 14-pin STQFN: 2 x 2.2 x 0.55 mm, 0.4 mm pitch 3 10 GPIO GPIO Applications 4 9 GPIO GND Personal Computers and Servers 6 7 PC Peripherals 5 8 GPIO GPIO Consumer Electronics Data Communications Equipment Handheld and Portable Electronics 14-pin STQFN (Top View) Block Diagram Pin 13 Pin 14 GPIO GPIO Pin 12 Pin 1 GPIO VDD Combination Function Macrocells Additional Logic Functions 2-bit 2-bit 2-bit LUT2 0 LUT2 1 LUT2 2 Pin 11 FILTER 0 FILTER 1 or DFF0 or DFF1 or DFF2 Pin 2 GPIO with with GPI Edge Edge ACMP0 Detect Detect 2-bit 3bit 3-bit LUT2 3 LUT3 0 LUT3 1 or PGEN or DFF3 or DFF4 3-bit 3-bit 3-bit LUT3 2 Programmable LUT3 3 LUT3 4 Pin 10 POR or DFF5 Pin 3 Delay or DFF6 or DFF7 GPIO ACMP1 GPIO 3-bit 3-bit 3-bit LUT3 5 or LUT3 6 or LUT3 7 or ASM CNT/DLY2 CNT/DLY3 CNT/DLY4 Vref 8 states 3-bit 3-bit 4-bit ACMP2 LUT3 8 or LUT3 9 or LUT4 0 or RC Oscillator Pin 9 2 I C Serial CNT/DLY5 CNT/DLY6 CNT/DLY0 Pin 4 GND Communication GPIO 25M Oscillator 4-bit 3-bit LUT4 1 or LUT3 10 or CNT/DLY1 Pipe Delay 8 Byte RAM + Crystal OTP Memory Oscillator Pin 5 Pin 8 GPIO GPIO Pin 6 Pin 7 SCL or SDA or GPIO GPIO 2020 Dialog Semiconductor Revision 1.14 Revised August 18, 2020 GPIO SCL/GPIO SDA/GPIO GPIOSLG46534 1.0 Overview The SLG46534 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins and the mac- rocells of the SLG46534. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following: Three Analog Comparators (ACMP) Nineteen Combination Function Macrocells Three Selectable DFF/Latch or 2-bit LUTs One Selectable Continuous DFF/Latch or 3-bit LUT Four Selectable DFF/Latch or 3-bit LUTs One Selectable Pipe Delay or 3-bit LUT One Selectable Programmable Pattern Generator or 2-bit LUT Five 8-bit delays/counters or 3-bit LUTs Two 16-bit delays/counters or 4-bit LUTs Two Deglitch Filters with Edge Detectors Asynchronous State Machine Eight States Flexible input logic from state transitions Serial Communications 2 I C Protocol compliant Pipe Delay 16 stage/3 output (Part of Combination Function Macrocell) Programmable Delay Two Oscillators (OSC) Configurable 25 kHz/2 MHz 25 MHz RC Oscillator Crystal Oscillator Power-On-Reset (POR) Eight Byte RAM + OTP User Memory 2 RAM Memory space that is readable and writable via I C User defined initial values transferred from OTP 2020 Dialog Semiconductor Revision 1.14 Page 1 of 174